Penryn, California
United States
88
2026-01-08
The entities that hold a legal rights for patent applications filed by inventor Eilert Sean S.:
Sean S. Eilert from Penryn, US has applied for patents for these inventions. The list has both pending applications and granted patents:
SIGNAL ROUTING BETWEEN MEMORY DIE AND LOGIC DIE FOR PERFORMING OPERATIONS
#2 | 2025-10-09READ REPLACEMENT VIA DATA RECONSTRUCTION BASED ON ACCESS PATTERNS
#3 | 2025-09-25REDUNDANT COMPUTING ACROSS PLANES
#4 | 2025-05-29PROCESSING-IN-MEMORY OPERATIONS, AND RELATED SYSTEMS AND METHODS
#5 | 2025-05-22PERFORMING PROCESSING-IN-MEMORY OPERATIONS RELATED TO PRE-SYNAPTIC SPIKE SIGNALS, AND RELATED METHODS AND SYSTEMS
#6 | 2025-05-22PROGRAMMABLE METADATA
#7 | 2025-03-27SIGNAL ROUTING BETWEEN MEMORY DIE AND LOGIC DIE
#8 | 2025-01-02SIGNAL ROUTING BETWEEN MEMORY DIE AND LOGIC DIE FOR MODE BASED OPERATIONS
#9 | 2024-12-19MEMORY DEVICE FOR WAFER-ON-WAFER FORMED MEMORY AND LOGIC
#10 | 2024-12-19PARITY-BASED ERROR MANAGEMENT FOR A PROCESSING SYSTEM
#11 | 2024-11-28ASSOCIATIVE COMPUTING FOR ERROR CORRECTION
#12 | 2024-10-31ADAPTIVE PARITY TECHNIQUES FOR A MEMORY DEVICE
#13 | 2024-10-03PROCESSING-IN-MEMORY OPERATIONS, AND RELATED APPARATUSES, SYSTEMS, AND METHODS
#14 | 2024-08-22IN-MEMORY ASSOCIATIVE PROCESSING FOR VECTORS
#15 | 2024-08-15PERFORMING PROCESSING-IN-MEMORY OPERATIONS RELATED TO PRE-SYNAPTIC SPIKE SIGNALS, AND RELATED METHODS AND SYSTEMS
#16 | 2024-07-11PERFORMING PROCESSING-IN-MEMORY OPERATIONS RELATED TO SPIKING EVENTS, AND RELATED METHODS, SYSTEMS AND DEVICES
#17 | 2024-06-20MEMORY DEVICE WITH ON-DIE CACHE
#18 | 2024-06-13METHODS FOR PERFORMING PROCESSING-IN-MEMORY OPERATIONS, AND RELATED SYSTEMS
#19 | 2024-06-13READ REPLACEMENT VIA DATA RECONSTRUCTION BASED ON ACCESS PATTERNS
#20 | 2024-05-09Redundant computing across planes
#21 | 2023-08-24Parity-based error management for a processing system
#22 | 2023-07-06Redundant computing across planes
#23 | 2023-06-29Associative computing for error correction
#24 | 2023-04-06Methods of performing processing-in-memory operations, and related devices and systems
#25 | 2023-03-09Error caching techniques for improved error correction in a memory device
#26 | 2023-03-02In-memory associative processing system
#27 | 2023-03-02In-memory associative processing for vectors
#28 | 2023-02-16Memory device for wafer-on-wafer formed memory and logic
#29 | 2023-02-16Signal routing between memory die and logic die for mode based operations
#30 | 2023-02-16TESTING MEMORY OF WAFER-ON-WAFER BONDED MEMORY AND LOGIC
#31 | 2023-02-16SIGNAL ROUTING BETWEEN MEMORY DIE AND LOGIC DIE FOR PERFORMING OPERATIONS
#32 | 2023-02-16Wafer-on-wafer formed memory and logic for genomic annotations
#33 | 2023-02-16FORMATION OF MEMORY DIE AND LOGIC DIE WITH WAFER-ON-WAFER BOND
#34 | 2023-02-16WAFER-ON-WAFER FORMED MEMORY AND LOGIC
#35 | 2023-02-16INPUT/OUTPUT CONNECTIONS OF WAFER-ON-WAFER BONDED MEMORY AND LOGIC
#36 | 2023-02-16MEMORY DIE AND LOGIC DIE WITH WAFER-ON-WAFER BOND
#37 | 2023-02-16Signal routing between memory die and logic die
#38 | 2023-01-12Programmable metadata
#39 | 2022-12-22Adaptive parity techniques for a memory device
#40 | 2022-12-08Memory accessing with auto-precharge
#41 | 2022-12-01Error control for content-addressable memory
#42 | 2022-09-22MEMORY CHIP CONNECTING A SYSTEM ON A CHIP AND AN ACCELERATOR CHIP
#43 | 2022-06-09Data recovery system for memory devices
#44 | 2022-05-19Mapping non-typed memory access to typed memory access
#45 | 2022-04-21Memory device with multiple row buffers
#46 | 2022-04-21Memory device with on-die cache
#47 | 2022-03-17INDICATION-BASED AVOIDANCE OF DEFECTIVE MEMORY CELLS
#48 | 2022-02-17Adaptive parity techniques for a memory device
#49 | 2022-02-17Error caching techniques for improved error correction in a memory device
#50 | 2022-02-17Programmable engine for data movement
#51 | 2021-12-23Methods of performing processing-in-memory operations, and related devices and systems
#52 | 2021-09-09Address obfuscation for memory
#53 | 2021-07-22Content addressable memory systems with content addressable memory buffers
#54 | 2021-06-24Memory accessing with auto-precharge
#55 | 2021-06-03Writing and querying operations in content addressable memory systems with content addressable memory buffers
#56 | 2021-03-25Exclusive or engine on random access memory
#57 | 2021-03-18ACCELERATOR CHIP CONNECTING A SYSTEM ON A CHIP AND A MEMORY CHIP
#58 | 2021-03-18Memory chip connecting a system on a chip and an accelerator chip
#59 | 2021-03-18Memory chip having an integrated data mover
#60 | 2021-03-18Mapping non-typed memory access to typed memory access
#61 | 2021-03-18Page table hooks to memory types
#62 | 2021-03-18FLEXIBLE PROVISIONING OF MULTI-TIER MEMORY
#63 | 2021-03-18Programmable engine for data movement
#64 | 2021-03-11Performing processing-in-memory operations related to pre-synaptic spike signals, and related methods and systems
#65 | 2021-03-11Performing processing-in-memory operations related to spiking events, and related methods, systems and devices
#66 | 2021-03-11Methods for performing processing-in-memory operations, and related memory devices and systems
#67 | 2021-03-11Methods for performing fused-multiply-add operations on serially allocated data within a processing-in-memory capable memory device, and related memory devices and systems
#68 | 2021-03-11Spatiotemporal fused-multiply-add, and related systems, methods and devices
#69 | 2021-03-04Error control for content-addressable memory
#70 | 2020-10-15Content addressable memory systems with content addressable memory buffers
#71 | 2020-10-15Writing and querying operations in content addressable memory systems with content addressable memory buffers
#72 | 2020-05-21Address obfuscation for memory
#73 | 2014-09-18Apparatus and methods for a distributed memory system including memory nodes
#74 | 2012-02-23Flexible selection command for non-volatile memory
#75 | 2010-06-24AUTONOMOUS MEMORY SUBSYSTEMS IN COMPUTING PLATFORMS
#76 | 2008-06-26High speed interface for non-volatile memory
#77 | 2008-06-26Flexible selection command for non-volatile memory
#78 | 2008-06-26High speed fanned out system architecture and input/output circuits for non-volatile memory
#79 | 2008-06-26Command-based control of NAND flash memory
#80 | 2008-02-05Dynamically mapping block-alterable memories
#81 | 2007-07-05Method and apparatus for single chip system boot
#82 | 2007-03-29Logging changes to blocks in a non-volatile memory
#83 | 2006-03-16Volatile storage based power loss recovery mechanism
#84 | 2006-01-05Virtual memory management system
#85 | 2005-12-22Partitionable memory device, system, and method
#86 | 2005-09-15Hardware stack for blocked nonvolatile memories
#87 | 2005-06-21Cluster based redundancy scheme for semiconductor memories
#88 | 2005-01-13Method and apparatus for generating a device ID for stacked devices
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