Inventor profile of:

Jaewon YANG

City:

Suwon-si

Country:

South Korea

Published Applications:

23

Last publication date:

2026-05-07

Top Assignees for applications by Jaewon YANG

The entities that hold a legal rights for patent applications filed by inventor YANG Jaewon:

Recent patent applications by YANG Jaewon

Jaewon YANG from Suwon-si, KR has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-05-07
US20260126730A1
Physics

PROCESS PROXIMITY CORRECTION (PPC) METHOD BASED ON DEEP LEARNING, AND SEMICONDUCTOR MANUFACTURING METHOD COMPRISING THE PPC METHOD

#2 | 2025-10-23
US20250328072A1
Physics

METHOD OF CORRECTING AN ERROR OF A LAYOUT OF A PATTERN AND METHOD OF FORMING A PATTERN USING THE SAME

#3 | 2025-10-16
US20250321478A1
Physics

DETECTION METHOD OF WEAK POINT AND VERIFICATION METHOD OF MASK QUALITY

#4 | 2025-09-25
US20250299298A1
Physics

PATTERN MODELING SYSTEM AND PATTERN MODELING METHOD

#5 | 2025-07-31
US20250244681A1
Physics

ELECTRONIC DEVICE AND METHOD OF OPERATION THEREOF

#6 | 2025-05-22
US20250165767A1
Physics

CROSSBAR ARRAY APPARATUSES BASED ON COMPRESSED-TRUNCATED SINGULAR VALUE DECOMPOSITION (C- TSVD) AND ANALOG MULTIPLY-ACCUMULATE (MAC) OPERATION METHODS USING THE SAME

#7 | 2025-05-22
US20250165693A1
Physics

MASK LAYOUT DESIGN METHOD AND MASK MANUFACTURING METHOD COMPRISING THE DESIGN METHOD

#8 | 2025-05-08
US20250147096A1
Physics

SUBSTRATE INSPECTION APPARATUS AND METHOD OF INSPECTING A SUBSTRATE USING THE SAME

#9 | 2025-04-17
US20250123243A1
Physics

SEMICONDUCTOR SUBSTRATE INSPECTION DEVICE

#10 | 2024-12-12
US20240413024A1
Electricity

PATTERN INSPECTION DEVICE AND PATTERN INSPECTION METHOD

#11 | 2024-11-21
US20240386635A1
Physics

ELECTRONIC DEVICE SUPPORTING MANUFACTURE OF SEMICONDUCTOR DEVICE AND OPERATING METHOD OF ELECTRONIC DEVICE

#12 | 2024-09-12
US20240303824A1
Physics

CONTOUR PROBABILITY PREDICTION METHOD

#13 | 2024-06-13
US20240193415A1
Physics

METHOD AND APPARATUS WITH SEMICONDUCTOR PATTERN CORRECTION

#14 | 2024-05-23
US20240168372A1
Physics

METHOD, APPARATUS, AND SYSTEM WITH RESIST IMAGE ESTIMATION

#15 | 2023-12-28
US20230418260A1
Physics

LITHOGRAPHY MODEL GENERATING METHOD BASED ON DEEP LEARNING, AND MASK MANUFACTURING METHOD INCLUDING THE LITHOGRAPHY MODEL GENERATING METHOD

#16 | 2023-09-07
US20230281792A1
Physics

OPERATING METHOD OF ELECTRONIC DEVICE INCLUDING PROCESSOR EXECUTING SEMICONDUCTOR LAYOUT SIMULATION MODULE BASED ON MACHINE LEARNING

#17 | 2023-09-07
US20230280646A1
Physics

CORNER ROUNDING METHOD OF OPC PATTERN BASED ON DEEP LEARNING, AND OPC METHOD AND MASK MANUFACTURING METHOD INCLUDING THE CORNER ROUNDING METHOD

#18 | 2023-06-22
US20230197460A1
Electricity

IMAGE-BASED SEMICONDUCTOR DEVICE PATTERNING METHOD USING DEEP NEURAL NETWORK

#19 | 2023-06-22
US20230196545A1
Physics

Computing device for predicting a profile using deep learning and operating method thereof

#20 | 2023-06-08
US20230177815A1
Physics

METHOD OF TRAINING SEMICONDUCTOR PROCESS IMAGE GENERATOR

#21 | 2022-04-07
US20220108159A1
Physics

Crossbar array apparatuses based on compressed-truncated singular value decomposition (C-TSVD) and analog multiply-accumulate (MAC) operation methods using the same

#22 | 2021-06-03
US20210165333A1
Physics

Reticle fabrication method and semiconductor device fabrication method including the same

#23 | 2020-05-28
US20200168271A1
Physics

Semiconductor memory device for supporting operation of neural network and operating method of semiconductor memory device

InventorID:

2746358 ⎘