Benoit de LESCURE

SYSTEM AND METHOD FOR INSERTION OF PIPELINE STAGES IN AND SYNTHESIS OF A NETWORK-ON-CHIP (NoC)

NETWORK ON CHIP BROADCASTERS USING DUPLICATED TRANSACTIONS

DESIGN TOOL FOR GENERATION OF DEADLOCK FREE NETWORK-ON-CHIP (NoC) WITHIN A SYSTEM-ON-CHIP (SoC)

MODIFICATION OF EXISTING NETWORK-ON-CHIPs (NoCs) USING INCREMENTAL MODIFICATIONS

ELECTRONIC DESIGN TOLL FOR GENERATION OF A NETWORK-ON-CHIP (NoC)

PERFORMING TRANSACTION AGGREGATION WITH AN AGGREGATOR IN A NETWORK-ON-CHIP (NoC)

CONNECTIVITY SYNTHESIS OF NETWORK-ON-CHIP (NoC) IN A MULTI-PROTOCOL SYSTEM-ON-CHIP (SOC)

SYSTEM AND METHOD FOR DEADLOCK DETECTION IN NETWORK-ON-CHIP (NoC) HAVING EXTERNAL DEPENDENCIES

SYSTEM AND METHOD TO GENERATE A NETWORK-ON-CHIP TOPOLOGY USING INCREMENTAL SYNTHESIS

AUTOMATIC CONFIGURATION OF PIPELINE MODULES IN A NETWORK-ON-CHIP (NoC)

SYSTEM AND METHOD FOR TRANSACTION BROADCAST IN A NETWORK ON CHIP

INCREMENTAL TOPOLOGY MODIFICATION OF A NETWORK-ON-CHIP

Constraints and objectives used in synthesis of a network-on-chip (NoC)

System and method to generate a network-on-chip (NoC) description using incremental topology synthesis

MODEL-DRIVEN APPROACH FOR FAILURE MODE, EFFECTS, AND DIAGNOSTIC ANALYSIS (FMEDA) AUTOMATION FOR HARDWARE INTELLECTUAL PROPERTY OF COMPLEX ELECTRONIC SYSTEMS

Automatic configuration of pipeline modules in an electronics system

Quality metrics for optimization tasks in generation of a network

Broadcast adapters in a network-on-chip

NETWORK-ON-CHIP (NoC) USING DEADLINE BASED ARBITRATION

SYNTHESIS OF A NETWORK-ON-CHIP (NoC) FOR INSERTION OF PIPELINE STAGES

SYSTEM AND METHOD FOR AREA AND TIMING ASSESSMENT OF A NETWORK-ON-CHIP (NoC) IMPLEMENTATION

System and method for editing a network-on-chip (NOC)

SYSTEM AND METHOD FOR DEADLOCK DETECTION IN NETWORK-ON-CHIP (NoC) HAVING EXTERNAL DEPENDENCIES

Constraints and objectives used in synthesis of a network-on-chip (NoC)

Switch with virtual channels for soft locking in a network-on-chip (NoC)

Incremental topology modification of a network-on-chip

System and method for synthesis of connectivity to an interconnect in a multi-protocol system-on-chip (SoC)

System and method for using soft lock with virtual channels in a network-on-chip (NoC)

Synthesis of a network-on-chip (NoC) using performance constraints and objectives

System and method for generation of quality metrics for optimization tasks in topology synthesis of a network

System and method to generate a network-on-chip (NoC) description using incremental topology synthesis

Topology synthesis of a network-on-chip (NoC)

SYSTEM AND METHOD FOR PERFORMING TRANSACTION AGGREGATION IN A NETWORK-ON-CHIP (NoC)

System and method for synthesis of a network-on-chip for deadlock-free transformation

Physically aware topology synthesis of a network

System and method for generating and using physical roadmaps in network synthesis

Multi-phase topology synthesis of a network-on-chip (NoC)

System and method for advanced detection of failures in a network-on-chip

System and method for transaction broadcast in a network on chip

Detection and isolation of faults to prevent propagation of faults in a resilient system

System and method for logic functional redundancy