Campbell, California
United States
136
2026-06-11
88
2026-06-02
These are the the leading inventors for applications assigned to Arteris, Inc:
Arteris, Inc based in Campbell, US has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:
ENSURING ARBITRATION FAIRNESS IN A NETWORK-ON-CHIP
#2 | 2026-06-02 ✅ Patent 12,645,595 granted on 2026-06-02Point-of-coherence exclusive monitor for a cache coherent interconnect for a multi-core electronic system
#3 | 2026-05-21SYSTEM AND METHOD FOR INSERTION OF PIPELINE STAGES IN AND SYNTHESIS OF A NETWORK-ON-CHIP (NoC)
#4 | 2026-05-21SHAPING A NETWORK-ON-CHIP TOPOLOGY PRIOR TO AUTOMATED TOPOLOGY SYNTHESIS
#5 | 2026-05-21STATIC ANALYSIS FOR BUFFER INSERTION IN A NETWORK-ON-CHIP TOPOLOGY
#6 | 2026-05-14COHERENT TRAFFIC ACCELERATION FOR A DIRECTORY-BASED MULTI-CORE ELECTRONIC SYSTEM
#7 | 2026-05-07SYSTEM AND METHOD FOR HANDLING MULTI-TARGET TRANSACTIONS IN AN ELETRONIC SYSTEM
#8 | 2026-04-16MULTIPLE INPUT, MULTIPLE OUTPUT COMPILER FOR PREPARING FILES FOR DESIGN OF A HARDWARE-SOFTWARE INTERFACE IN AN ELECTRONIC SYSTEM
#9 | 2026-01-08METHOD FOR CONNECTING PORTS OF A NETWORK-ON-CHIP (NoC) VIA REGULAR EXPRESSIONS
#10 | 2026-01-08DESIGN TOOL FOR CONNECTING PORTS OF A NETWORK-ON-CHIP (NoC) VIA REGULAR EXPRESSIONS
#11 | 2026-01-08DESIGN TOOL FOR USING SUB-ARCHITECTURES OF A MAIN ARCHITECTURE IN NETWORK-ON-SHIP DESIGN DISTRIBUTION AND ASSEMBLY
#12 | 2026-01-08NETWORK ON CHIP BROADCASTERS USING DUPLICATED TRANSACTIONS
#13 | 2026-01-06 ✅ Patent 12,517,829 granted on 2026-01-06Processing writes to multiple targets in a directory-based cache coherent electronic system
#14 | 2026-01-01REINFORCED LEARNING FOR TOPOLOGY GENERATION OF A NETWORK-ON-CHIP
#15 | 2026-01-01DESIGN TOOL FOR GENERATION OF A NETWORK-ON-CHIP (NOC) INCLUDING INSERTION OF ADAPTERS IN A PATH
#16 | 2026-01-01DEADLOCK-FREE MODIFICATION TO NETWORK-ON-CHIP TOPOLOGY
#17 | 2026-01-01VIRTUAL BRIDGE FOR DESIGN OF AN INTEGRATED CIRCUIT
#18 | 2025-12-04DESIGN TOOL FOR GENERATION OF DEADLOCK FREE NETWORK-ON-CHIP (NoC) WITHIN A SYSTEM-ON-CHIP (SoC)
#19 | 2025-10-30DESIGN TOOL USING MACHINE LEARNING MODELS FOR INTERACTIVE ROUTE DETERMINATION IN A NETWORK-ON-CHIP
#20 | 2025-10-30DESIGN TOOL USING MACHINE LEARNING FOR INCREMENTAL PLACEMENT OF ELEMENTS ON FLOORPLAN
#21 | 2025-10-09BROADCASTER WITH BUFFERING FOR NETWORK ON CHIP (NoC)
#22 | 2025-10-09SYSTEM AND METHOD FOR USING INTERFACE PROTECTION PARAMETERS
#23 | 2025-09-18MODIFICATION OF EXISTING NETWORK-ON-CHIPs (NoCs) USING INCREMENTAL MODIFICATIONS
#24 | 2025-08-21ELECTRONIC DESIGN TOLL FOR GENERATION OF A NETWORK-ON-CHIP (NoC)
#25 | 2025-07-31PERFORMING TRANSACTION AGGREGATION WITH AN AGGREGATOR IN A NETWORK-ON-CHIP (NoC)
#26 | 2025-07-24CONNECTIVITY SYNTHESIS OF NETWORK-ON-CHIP (NoC) IN A MULTI-PROTOCOL SYSTEM-ON-CHIP (SOC)
#27 | 2025-07-17SYSTEM AND METHOD FOR DEADLOCK DETECTION IN NETWORK-ON-CHIP (NoC) HAVING EXTERNAL DEPENDENCIES
#28 | 2025-05-29TOOL FOR FAULT DETECTION AND CLASSIFICATION IN DESIGN AND GENERATION OF NETWORK-ON-CHIP (NoCs)
#29 | 2025-05-29SYSTEM AND METHOD FOR TRAINING A NEURAL LEARNING MODEL FOR PREDICTING PERFORMANCE, POWER AND AREA BEHAVIOR OF IP COMPONENTS IN INTEGRATED CIRCUIT DESIGN
#30 | 2025-05-15SYSTEM AND METHOD TO GENERATE A NETWORK-ON-CHIP TOPOLOGY USING INCREMENTAL SYNTHESIS
#31 | 2025-04-10SYSTEM AND METHOD FOR GENERATION OF NETWORKS-ON-CHIP (NoCs) USING INCREMENTAL TOPOLOGY SYNTHESIS FOR OPTIMIZATION OF SWITCHES
#32 | 2025-04-10 ✅ Patent 12,657,155 granted on 2026-06-16SYSTEM AND METHOD FOR GENERATION OF NETWORKS-ON-CHIP (NoCs)
#33 | 2025-03-27SYSTEM AND METHOD TO CONTROL TASKS EXECUTION IN A SYSTEM-ON-CHIP (SoC) BY OBSERVING PACKETS IN A NETWORK-ON-CHIP (NoC)
#34 | 2025-03-27SYSTEM AND METHOD FOR MANAGING EVENT MESSAGES IN A CACHE COHERENT INTERCONNECT
#35 | 2024-12-26TOOL FOR SUPPORTING USE OF REGULAR NETWORK TOPOLOGIES IN GENERATING A NETWORK-ON-CHIP TOPOLOGY
#36 | 2024-12-12AUTOMATIC CONFIGURATION OF PIPELINE MODULES IN A NETWORK-ON-CHIP (NoC)
#37 | 2024-12-05SYSTEM AND METHOD FOR GENERATION OF A NETWORK USING PHYSICAL AWARENESS DATA FROM AN IMAGE OF A CHIP FLOORPLAN
#38 | 2024-12-05DESIGN TOOL FOR INTERACTIVE WIRE ROUTING DURING THE GENERATION OF A NETWORK-ON-CHIP
#39 | 2024-12-05DESIGN TOOL FOR AUTOMATED PLACEMENT CONSTRAINT GENERATION, ADAPTER INSERTION PROCESS, AND LOCAL AND GLOBAL CONGESTION CAPTURE
#40 | 2024-12-05DESIGN TOOL FOR INTERACTIVE INCREMENTAL PLACEMENT OF ELEMENTS ON FLOORPLAN
#41 | 2024-11-14 ✅ Patent 12,411,801 granted on 2025-09-09SYSTEM AND METHOD FOR TRANSACTION BROADCAST IN A NETWORK ON CHIP
#42 | 2024-10-24PROCESS FOR GENERATING PHYSICAL IMPLEMENTATION GUIDANCE DURING THE SYNTHESIS OF A NETWORK-ON-CHIP
#43 | 2024-08-01 ✅ Patent 12,348,382 granted on 2025-07-01INCREMENTAL TOPOLOGY MODIFICATION OF A NETWORK-ON-CHIP
#44 | 2024-07-18SYSTEM AND METHOD FOR DETERMINISTIC AND INCREMENTAL PHYSICALLY-AWARE NETWORK-ON-CHIP GENERATION
#45 | 2024-07-04 ✅ Patent 12,135,928 granted on 2024-11-05Constraints and objectives used in synthesis of a network-on-chip (NoC)
#46 | 2024-07-04 ✅ Patent 12,210,810 granted on 2025-01-28System and method for predicting performance, power and area behavior of soft IP components in integrated circuit design
#47 | 2024-06-27 ✅ Patent 12,204,833 granted on 2025-01-21System and method to generate a network-on-chip (NoC) description using incremental topology synthesis
#48 | 2024-05-16 ✅ Patent 12,340,156 granted on 2025-06-24SYSTEM AND METHOD FOR USING INTERFACE PROTECTION PARAMETERS
#49 | 2023-11-30 ✅ Patent 12,335,134 granted on 2025-06-17NETWORK-ON-CHIP (NoC) WITH A BROADCAST SWITCH SYSTEM
#50 | 2023-10-26MODEL-DRIVEN APPROACH FOR FAILURE MODE, EFFECTS, AND DIAGNOSTIC ANALYSIS (FMEDA) AUTOMATION FOR HARDWARE INTELLECTUAL PROPERTY OF COMPLEX ELECTRONIC SYSTEMS
#51 | 2023-10-12 ✅ Patent 12,067,335 granted on 2024-08-20Automatic configuration of pipeline modules in an electronics system
#52 | 2023-10-12 ✅ Patent 12,072,805 granted on 2024-08-27System and method to enter and exit a cache coherent interconnect
#53 | 2023-09-14 ✅ Patent 11,782,834 granted on 2023-10-10System and method for round robin arbiters in a network-on-chip (NoC)
#54 | 2023-05-18 ✅ Patent 11,784,909 granted on 2023-10-10Quality metrics for optimization tasks in generation of a network
#55 | 2023-05-04 ✅ Patent 12,164,428 granted on 2024-12-10System and method for event messages in a cache coherent interconnect
#56 | 2023-05-04 ✅ Patent 12,038,866 granted on 2024-07-16Broadcast adapters in a network-on-chip
#57 | 2023-04-13NETWORK-ON-CHIP (NoC) USING DEADLINE BASED ARBITRATION
#58 | 2023-04-13 ✅ Patent 12,055,588 granted on 2024-08-06Testbenches for electronic systems with automatic insertion of verification features
#59 | 2023-04-13 ✅ Patent 12,166,643 granted on 2024-12-10Mechanism to control order of tasks execution in a system-on-chip (SoC) by observing packets in a network-on-chip (NoC)
#60 | 2023-04-06 ✅ Patent 12,524,590 granted on 2026-01-13SYNTHESIS OF A NETWORK-ON-CHIP (NoC) FOR INSERTION OF PIPELINE STAGES
#61 | 2023-03-30 ✅ Patent 12,450,036 granted on 2025-10-21SYSTEM AND METHOD FOR SCRIPTING GENERATORS
#62 | 2023-03-30SYSTEM AND METHOD FOR AREA AND TIMING ASSESSMENT OF A NETWORK-ON-CHIP (NoC) IMPLEMENTATION
#63 | 2023-03-30UNIQUE IDENTIFIER CREATION AND MANAGEMENT FOR ELABORATED PLATFORM
#64 | 2023-03-30 ✅ Patent 12,093,177 granted on 2024-09-17Multi-level partitioned snoop filter
#65 | 2023-03-30 ✅ Patent 12,184,499 granted on 2024-12-31System and method for editing a network-on-chip (NOC)
#66 | 2023-03-30 ✅ Patent 12,438,829 granted on 2025-10-07SYSTEM AND METHOD FOR DEADLOCK DETECTION IN NETWORK-ON-CHIP (NoC) HAVING EXTERNAL DEPENDENCIES
#67 | 2023-03-16 ✅ Patent 12,026,095 granted on 2024-07-02Cache coherent system implementing victim buffers
#68 | 2023-01-26 ✅ Patent 12,511,466 granted on 2025-12-30SYSTEM AND METHOD FOR GENERATION OF A REPORT AND DEBUG OF ADDRESS TRANSFORMATIONS IN ELECTRONIC SYSTEMS DESCRIBED WITH IP-XACT STANDARD
#69 | 2023-01-19 ✅ Patent 11,836,427 granted on 2023-12-05Constraints and objectives used in synthesis of a network-on-chip (NoC)
#70 | 2022-11-17 ✅ Patent 11,838,211 granted on 2023-12-05System and method to determine optimal path(s) and use load balancing in an interconnect
#71 | 2022-11-03 ✅ Patent 11,805,080 granted on 2023-10-31System and method for data loss and data latency management in a network-on-chip with buffered switches
#72 | 2022-09-22 ✅ Patent 11,831,557 granted on 2023-11-28Switch with virtual channels for soft locking in a network-on-chip (NoC)
#73 | 2022-09-15 ✅ Patent 11,956,127 granted on 2024-04-09Incremental topology modification of a network-on-chip
#74 | 2022-08-18 ✅ Patent 12,289,384 granted on 2025-04-29System and method for synthesis of connectivity to an interconnect in a multi-protocol system-on-chip (SoC)
#75 | 2022-07-14 ✅ Patent 11,675,942 granted on 2023-06-13Optimization of parameters for synthesis of a topology using a discriminant function module
#76 | 2022-06-30 ✅ Patent 11,757,798 granted on 2023-09-12Management of a buffered switch having virtual channels for data transmission within a network
#77 | 2022-06-30 ✅ Patent 11,489,786 granted on 2022-11-01Queue management system, starvation and latency management system, and methods of use
#78 | 2022-06-30 ✅ Patent 11,368,402 granted on 2022-06-21System and method for using soft lock with virtual channels in a network-on-chip (NoC)
#79 | 2022-06-30 ✅ Patent 11,729,088 granted on 2023-08-15Broadcast switch system in a network-on-chip (NoC)
#80 | 2022-06-30 ✅ Patent 11,449,655 granted on 2022-09-20Synthesis of a network-on-chip (NoC) using performance constraints and objectives
#81 | 2022-06-30 ✅ Patent 11,409,934 granted on 2022-08-09Generation of hardware design using a constraint solver module for topology synthesis
#82 | 2022-06-30 ✅ Patent 11,573,822 granted on 2023-02-07System and method for generating and using a context block based on system parameters
#83 | 2022-06-23 ✅ Patent 11,601,357 granted on 2023-03-07System and method for generation of quality metrics for optimization tasks in topology synthesis of a network
#84 | 2022-06-16 ✅ Patent 11,748,535 granted on 2023-09-05System and method to generate a network-on-chip (NoC) description using incremental topology synthesis
#85 | 2022-06-09 ✅ Patent 11,847,394 granted on 2023-12-19System and method for using interface protection parameters
#86 | 2022-03-22 ✅ Patent 11,281,827 granted on 2022-03-22Optimization of parameters for synthesis of a topology using a discriminant function module
#87 | 2021-12-30 ✅ Patent 12,237,980 granted on 2025-02-25Topology synthesis of a network-on-chip (NoC)
#88 | 2021-12-28 ✅ Patent 11,210,445 granted on 2021-12-28System and method for interface protection
#89 | 2021-12-09 ✅ Patent 12,380,055 granted on 2025-08-05SYSTEM AND METHOD FOR PERFORMING TRANSACTION AGGREGATION IN A NETWORK-ON-CHIP (NoC)
#90 | 2021-10-14 ✅ Patent 11,418,448 granted on 2022-08-16System and method for synthesis of a network-on-chip to determine optimal path with load balancing
#91 | 2021-07-01 ✅ Patent 11,665,776 granted on 2023-05-30System and method for synthesis of a network-on-chip for deadlock-free transformation
#92 | 2021-07-01 ✅ Patent 11,121,933 granted on 2021-09-14Physically aware topology synthesis of a network
#93 | 2021-07-01 ✅ Patent 11,558,259 granted on 2023-01-17System and method for generating and using physical roadmaps in network synthesis
#94 | 2021-07-01 ✅ Patent 11,657,203 granted on 2023-05-23Multi-phase topology synthesis of a network-on-chip (NoC)
#95 | 2021-07-01 ✅ Patent 11,755,797 granted on 2023-09-12System and method for predicting performance, power and area behavior of soft IP components in integrated circuit design
#96 | 2021-06-17 ✅ Patent 11,294,757 granted on 2022-04-05System and method for advanced detection of failures in a network-on-chip
#97 | 2021-05-20 ✅ Patent 11,436,185 granted on 2022-09-06System and method for transaction broadcast in a network on chip
#98 | 2021-03-25 ✅ Patent 11,513,892 granted on 2022-11-29System and method for using a directory to recover a coherent system from an uncorrectable error
#99 | 2021-03-18 ✅ Patent 11,385,957 granted on 2022-07-12System for memory access bandwidth management using ECC
#100 | 2020-07-09 ✅ Patent 11,080,191 granted on 2021-08-03Configurable snoop filters for cache coherent systems
Also check out Arteris, Inc.'s (Campbell, United States) applicant profile with 125 patent applications submitted.
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