Marcel WALL

GLASS CORE EDGE TREATMENTS FOR HYBRID PANELS IN DEVICE PACKAGING

PASSIVATION BOUNDARY DEFECTS FOR REDUCED LEAKAGE CURRENT CAPACITOR DIELECTRIC MATERIALS

CARBON NANOFIBER CAPACITOR APPARATUS AND RELATED METHODS

THROUGH GLASS VIAS WITH COMPLIANT LAYER FOR INTEGRATED CIRCUIT DEVICE PACKAGES

HYBRID METALLIZATION SURFACES FOR INTEGRATED CIRCUIT PACKAGES

GLASS-INTEGRATED INDUCTORS IN INTEGRATED CIRCUIT PACKAGES

ELECTRONIC SUBSTRATES HAVING EMBEDDED INDUCTORS

PHOTONIC INTEGRATED CIRCUIT PACKAGES AND METHODS OF MANUFACTURING THE SAME

SUBSTRATE PACKAGE-INTEGRATED OXIDE CAPACITORS AND RELATED METHODS

THIN FILM CAPACITOR (TFC) ARCHITECTURES FOR PACKAGE SUBSTRATES

THIN FILM CAPACITORS (TFCS) IN ETCHED BACK DEEP VIA

DIRECT PLATING OF COPPER ON DIELECTRICS FOR GLASS CORE PLATING

METHOD OF FORMING A PACKAGE SUBSTRATE

METALLIZATION SURFACE TREATMENT FOR INTEGRATED CIRCUIT PACKAGES

SUBSTRATES HAVING ADHESION PROMOTOR LAYERS AND RELATED METHODS

SILICIDE AND SILICON NITRIDE LAYERS BETWEEN A DIELECTRIC AND COPPER

EDGE DELAMINATION AND CRACK PREVENTION METHODS FOR SINX AND TI-CU ENABLED PACKAGES

ORGANIC ADHESION PROMOTOR FOR DIELECTRIC ADHESION TO A COPPER TRACE

SURFACE FUNCTIONALIZATION OF SINX THIN FILM BY WET ETCHING FOR IMPROVED ADHESION OF METAL-DIELECTRIC FOR HSIO

PLASMA-INDUCED SURFACE FUNCTIONALIZATION OF SINX THIN FILM FOR IMPROVED ADHESION OF METAL-DIELECTRIC FOR HSIO

MODIFICATION OF SINX THIN FILM FOR IMPROVED ADHESION OF METAL-DIELECTRICS FOR HSIO PACKAGING

THROUGH GLASS VIA WITH A METAL WALL

CAPACITORS IN THROUGH GLASS VIAS

METHODS AND APPARATUS TO IMPROVE ADHESION BETWEEN METALS AND DIELECTRICS IN CIRCUIT DEVICES

Dielectric-to-metal adhesion promotion material

Selectively roughened copper architectures for low insertion loss conductive features

Electronic substrates having embedded inductors

ELECTROLESS PLATING PROCESS

MULTIPLE LAYER COPPER SEEDING

COPPER INTERFACE FEATURES FOR HIGH SPEED INTERCONNECT APPLICATIONS

CONTROLLED ORGANIC LAYERS TO ENHANCE ADHESION TO ORGANIC DIELECTRICS AND PROCESS FOR FORMING SUCH

Hybrid fine line spacing architecture for bump pitch scaling

Selective metal deposition by patterning direct electroless metal plating

Package architecture with improved via drill process and method for forming such package

Interfacial layer for high resolution lithography (HRL) and high speed input/output (IO or I/O) architectures