Suman Datta

GATE ELECTRODE HAVING A CAPPING LAYER

GATE ELECTRODE HAVING A CAPPING LAYER

Method for fabricating transistor with thinned channel

Gate electrode having a capping layer

Method for fabricating transistor with thinned channel

Method for fabricating transistor with thinned channel

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

Extreme high mobility CMOS logic

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

FABRICATION OF CHANNEL WRAPAROUND GATE STRUCTURE FOR FIELD-EFFECT TRANSISTOR

Semiconductor device structures and methods of forming semiconductor structures

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

Method for fabricating transistor with thinned channel

Gate electrode having a capping layer

Extreme high mobility CMOS logic

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

Forming arsenide-based complementary logic on a single substrate

Semiconductor device structures and methods of forming semiconductor structures

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

Extreme high mobility CMOS logic

Gate electrode having a capping layer

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

Strain inducing semiconductor regions

Semiconductor device structures and methods of forming semiconductor structures

Strain-inducing semiconductor regions

Extreme high mobility CMOS logic

Gate electrode having a capping layer

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

Extreme high mobility CMOS logic

Strain inducing semiconductor regions

Semiconductor device structures and methods of forming semiconductor structures

Transistor gate electrode having conductor material layer

CMOS devices with a single work function gate electrode and method of fabrication

Gate electrode having a capping layer

FABRICATION OF CHANNEL WRAPAROUND GATE STRUCTURE FOR FIELD-EFFECT TRANSISTOR

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

Inducing strain in the channels of metal gate transistors

Capacitor, method of increasing a capacitance area of same, and system containing same

Method for fabricating transistor with thinned channel

Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication

Transistor gate electrode having conductor material layer

Strain-inducing semiconductor regions

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

Three-dimensional integrated circuit for analyte detection

Forming integrated circuits with replacement metal gate electrodes

Mechanism for forming a remote delta doping layer of a quantum well structure

Tri-gate transistor device with stress incorporation layer and method of fabrication

Substrate band gap engineered multi-gate pMOS devices

Increasing the surface area of a memory cell capacitor

Forming abrupt source drain metal gate transistors

High mobility tri-gate devices and methods of fabrication

Field effect transistor with metal source/drain regions

Transistor gate electrode having conductor material layer

Tensile strained NMOS transistor using group III-N source/drain regions

Dopant confinement in the delta doped layer using a dopant segregration barrier in quantum well structures

Directing carbon nanotube growth

CMOS DEVICE WITH METAL AND SILICIDE GATE ELECTRODES AND A METHOD FOR MAKING IT

Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate

Semiconductor device structures and methods of forming semiconductor structures

METAL GATE DEVICE WITH REDUCED OXIDATION OF A HIGH-K GATE DIELECTRIC

Reducing Ambipolar Conduction in Carbon Nanotube Transistors

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

Gate electrode having a capping layer

Dielectric interface for group III-V semiconductor device

Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby

Method to introduce uniaxial strain in multigate nanoscale transistors by self aligned SI to SIGE conversion processes and structures formed thereby

Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress

Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication

Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

Semiconductor device with a high-k gate dielectric and a metal gate electrode

Method for making a semiconductor device having a high-k gate dielectric

Forming dual metal complementary metal oxide semiconductor integrated circuits

Semiconductor device with reduced fringe capacitance

High hole mobility semiconductor device

Tunneling field effect transistor using angled implants for forming asymmetric source/drain regions

Block contact architectures for nanoscale channel transistors

Increasing the surface area of a memory cell capacitor

Hetero-bimos injection process for non-volatile flash memory

Multi-gate structure and method of doping same

On-chip memory cell and method of manufacturing same

Capacitor, method of increasing a capacitance area of same, and system containing same

Transistor having tensile strained channel and system including same

Mechanism for forming a remote delta doping layer of a quantum well structure

Reducing oxidation under a high K gate dielectric

Buffer architecture formed on a semiconductor wafer

Forming arsenide-based complementary logic on a single substrate

Lateral undercut of metal gate in SOI device

SRAM and logic transistors with variable height multi-gate transistor architecture

Method of combining floating body cell and logic transistors

Dopant confinement in the delta doped layer using a dopant segregation barrier in quantum well structures

Transistor for non volatile memory devices having a carbon nanotube channel and electrically floating quantum dots in its gate dielectric

INSULATED GATE FOR GROUP III-V DEVICES

Strain-inducing semiconductor regions

Method for making a semiconductor device having a high-k dielectric layer and a metal gate electrode

CMOS device with metal and silicide gate electrodes and a method for making it

Sb-based CMOS devices

Forming high-k dielectric layers on smooth substrates

Methods for uniform doping of non-planar transistor structures

Dual crystal orientation circuit devices on the same substrate