Beaverton, Oregon
United States
65
2019-08-08
The entities that hold a legal rights for patent applications filed by inventor Chau Robert:
Robert Chau from Beaverton, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Group III-N transistors for system on chip (SOC) architecture integrating power management and radio frequency circuits
#2 | 2019-07-25CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture
#3 | 2019-05-30Group III-N nanowire transistors
#4 | 2017-10-05Group III-N nanowire transistors
#5 | 2017-09-14High voltage field effect transistors
#6 | 2017-08-10CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture
#7 | 2017-07-20Self-aligned gate last III-N transistors
#8 | 2016-11-24High electron mobility transistor (HEMT) and method of fabrication
#9 | 2016-10-27Group III-N nanowire transistors
#10 | 2016-03-17High voltage field effect transistors
#11 | 2016-03-03Group III-N nanowire transistors
#12 | 2015-11-12CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture
#13 | 2013-11-28Apparatus and methods for improving parallel conduction in a quantum well device
#14 | 2013-11-21High voltage field effect transistors
#15 | 2013-10-24Group III-N nanowire transistors
#16 | 2013-10-24Non-planar III-N transistor
#17 | 2013-10-17Group III-N transistors for system on chip (SOC) architecture integrating power management and radio frequency circuits
#18 | 2013-10-17CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture
#19 | 2013-06-20Strained transistor integration for CMOS
#20 | 2012-12-27Apparatus and methods for improving parallel conduction in a quantum well device
#21 | 2012-03-29Non-planar quantum well device having interfacial layer and method of forming same
#22 | 2012-02-09Apparatus and methods for improving parallel conduction in a quantum well device
#23 | 2011-08-04Transistor gate electrode having conductor material layer
#24 | 2011-02-17Semiconductor on insulator
#25 | 2011-01-27Transistor gate electrode having conductor material layer
#26 | 2010-11-11Methods of forming nanodots using spacer patterning techniques and structures formed thereby
#27 | 2010-09-16Apparatus and methods for improving parallel conduction in a quantum well device
#28 | 2010-07-01Isolated Germanium nanowire on Silicon fin
#29 | 2010-02-25Strained transistor integration for CMOS
#30 | 2010-02-18Semiconductor on insulator apparatus
#31 | 2009-12-24Transistor gate electrode having conductor material layer
#32 | 2009-04-02CONTROLLED INTERMIXING OF HFO2 AND ZRO2 DIELECTRICS ENABLING HIGHER DIELECTRIC CONSTANT AND REDUCED GATE LEAKAGE
#33 | 2009-01-06Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby
#34 | 2008-12-11Semiconductor on insulator apparatus
#35 | 2008-10-02High density memory
#36 | 2008-09-23Semiconductor on insulator apparatus and method
#37 | 2008-09-04Buffer architecture formed on a semiconductor wafer
#38 | 2008-07-17Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
#39 | 2008-07-03Method of combining floating body cell and logic transistors
#40 | 2008-06-26Transistor for non volatile memory devices having a carbon nanotube channel and electrically floating quantum dots in its gate dielectric
#41 | 2008-04-10Methods for uniform doping of non-planar transistor structures
#42 | 2008-01-17Method and apparatus to prevent lateral oxidation in a transistor utilizing an ultra thin oxygen-diffusion barrier
#43 | 2007-11-15TRI-GATE TRANSISTORS AND METHODS TO FABRICATE SAME
#44 | 2007-07-26Transistor gate electrode having conductor material layer
#45 | 2007-05-24Transistor for non volatile memory devices having a carbon nanotube channel and electrically floating quantum dots in its gate dielectric
#46 | 2007-03-01Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer
#47 | 2006-07-20Non-planar MOS structure with a strained channel region
#48 | 2006-07-20Non-planar MOS structure with a strained channel region
#49 | 2006-05-16Pre-etch implantation damage for the removal of thin film layers
#50 | 2006-03-23U-gate transistors and methods of fabrication
#51 | 2006-02-16Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
#52 | 2006-02-14Metal-gate electrode for CMOS transistor applications
#53 | 2006-01-26Metalgate electrode for PMOS transistor
#54 | 2005-12-13Double-gate transistor with enhanced carrier mobility
#55 | 2005-12-08Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby
#56 | 2005-07-21Semiconductor device having a metal gate electrode
#57 | 2005-07-21Tri-gate transistors and methods to fabricate same
#58 | 2005-07-07Transistor gate electrode having conductor material layer
#59 | 2005-06-30Method of fabricating an ultra-narrow channel semiconductor device
#60 | 2005-06-23Strained transistor integration for CMOS
#61 | 2005-06-09Non-silicon semiconductor and high-k gate dielectric metal oxide semiconductor field effect transistors
#62 | 2005-05-31Non-silicon semiconductor and high-k gate dielectric metal oxide semiconductor field effect transistors
#63 | 2005-05-10Method for making a semiconductor device having a metal gate electrode
#64 | 2005-02-10Method for making a semiconductor device having a high-k gate dielectric
#65 | 2005-02-03Method of fabricating an ultra-narrow channel semiconductor device
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