Inventor profile of:

Mark I. Gardner

City:

Austin, Texas

Country:

United States

Published Applications:

16

Last publication date:

2026-03-26

Top Assignees for applications by Mark I. Gardner

The entities that hold a legal rights for patent applications filed by inventor Gardner Mark I.:

Recent patent applications by Gardner Mark I.

Mark I. Gardner from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-03-26
US20260088690A1
Electricity

ELECTRICAL ENERGY PRODUCED BY ROTATING MAGNETS

#2 | 2026-02-26
US20260060040A1
Electricity

CONTACTLESS WAFER POSITIONING CARRIER DESIGN

#3 | 2026-01-22
US20260022929A1
Physics

METAL RECESS DEPTH MEASUREMENTS BY CAPACITOR TEST STRUCTURE

#4 | 2025-12-25
US20250391808A1
Electricity

WAFER OVERLAY REGISTRATION IN HYBRID BONDING

#5 | 2025-09-25
US20250297969A1
Physics

REFLECTING NON-PLANAR SURFACES INTEGRATED WITH LASER SCAN FOR POSEIDON TOOL INTEGRATION

#6 | 2025-09-18
US20250290745A1
Physics

APPARATUS AND METHOD FOR DETERMINING THE SURFACE PROFILE OF A SEMICONDUCTOR SUBSTRATE USING A LASER SCANNING TECHNIQUE

#7 | 2025-08-28
US20250273619A1
Electricity

METHOD OF HYBRID BONDING USING DIE DISTRIBUTION MODEL

#8 | 2025-05-22
US20250167024A1
Electricity

WAFER SUPPORT FOR MEASURING WAFER GEOMETRY

#9 | 2025-05-22
US20250167023A1
Electricity

DEVICE AND METHOD FOR DETERMINING WAFER BOW

#10 | 2025-05-22
US20250164230A1
Physics

CONTACTLESS CAPACITIVE MEASUREMENT TOOL WITH IMPROVED THROUGHPUT AND ACCURACY

#11 | 2025-04-17
US20250123090A1
Physics

DEVICE AND METHOD FOR DETERMINING WAFER BOW

#12 | 2025-02-13
US20250056810A1
Electricity

SEMICONDUCTOR DEVICES WITH VERTICAL TRANSISTORS AND FERROELECTRIC CAPACITORS

#13 | 2025-01-30
US20250040202A1
Electricity

METHODS AND DEVICES FOR VERTICAL CONNECTION WITH INTERNAL EPITAXIAL STRUCTURE

#14 | 2025-01-23
US20250031400A1
Electricity

FORKSHEET SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME

#15 | 2025-01-09
US20250015045A1
Electricity

METHOD FOR STACKING INTEGRATED CIRCUIT WAFERS AND DIES

#16 | 2020-12-31
US20200411518A1
Electricity

Multiple nano layer transistor layers with different transistor architectures for improved circuit layout and performance

InventorID:

2953085 ⎘