Beaverton, Oregon
United States
16
2026-01-22
The entities that hold a legal rights for patent applications filed by inventor KUMAR Nitesh:
Nitesh KUMAR from Beaverton, US has applied for patents for these inventions. The list has both pending applications and granted patents:
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING SOURCE OR DRAIN STRUCTURES WITH REGROWN CENTRAL PORTIONS
#2 | 2023-12-28SELF-ALIGNED EMBEDDED SOURCE AND DRAIN CONTACTS
#3 | 2023-12-14SOURCE AND DRAIN CONTACTS FORMED USING SACRIFICIAL REGIONS OF SOURCE AND DRAIN
#4 | 2023-12-073D SOURCE AND DRAIN CONTACTS TUNED FOR VERTICALLY STACKED PMOS AND NMOS
#5 | 2023-12-073D SOURCE AND DRAIN CONTACTS TUNED FOR PMOS AND NMOS
#6 | 2023-12-07SELECTIVE REMOVAL OF CHANNEL BODIES IN STACKED GATE-ALL-AROUND (GAA) DEVICE STRUCTURES
#7 | 2023-06-29GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING SOURCE OR DRAIN STRUCTURES WITH SUBSTRATE CONNECTION PORTIONS
#8 | 2023-06-22GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING SOURCE OR DRAIN STRUCTURES WITH REGROWN CENTRAL PORTIONS
#9 | 2023-06-22FORMATION OF CAVITY SPACER AND SOURCE-DRAIN EPITAXIAL GROWTH FOR SCALING OF GATE-ALL-AROUND TRANSISTORS
#10 | 2023-06-15STACKED TRANSISTORS WITH REMOVED EPI BARRIER
#11 | 2023-05-25GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING FIN STACK ISOLATION
#12 | 2022-12-29LATERAL CONFINEMENT OF SOURCE DRAIN EPITAXIAL GROWTH IN NON-PLANAR TRANSISTOR FOR CELL HEIGHT SCALING
#13 | 2022-12-29GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING GATE HEIGHT REDUCTION BY FIN HARD MASK REMOVAL POST DUMMY GATE PATTERNING REMOVAL
#14 | 2022-12-29NANORIBBON SUBFIN ISOLATION BY BACKSIDE SILICON SUBSTRATE REMOVAL WITH EPI PROTECTION
#15 | 2021-09-30Gate-all-around integrated circuit structures having fin stack isolation
#16 | 2020-12-31DEPOP using cyclic selective spacer etch
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