Los Gatos, California
United States
57
2018-09-13
The entities that hold a legal rights for patent applications filed by inventor Ranade Pushkar:
Pushkar Ranade from Los Gatos, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Semiconductor structure with multiple transistors having various threshold voltages
#2 | 2017-11-09Buried channel deeply depleted channel transistor
#3 | 2017-05-18Semiconductor structure with multiple transistors having various threshold voltages
#4 | 2017-02-09Advanced transistors with punch through suppression
#5 | 2017-02-09Reducing or eliminating pre-amorphization in transistor manufacture
#6 | 2017-01-26Buried channel deeply depleted channel transistor
#7 | 2017-01-12Low power semiconductor transistor structure and method of fabrication thereof
#8 | 2016-11-17Transistor with threshold voltage set notch and method of fabrication thereof
#9 | 2016-10-25Buried channel deeply depleted channel transistor
#10 | 2016-10-20CMOS Structures and Processes Based on Selective Thinning
#11 | 2016-09-15Reducing or eliminating pre-amorphization in transistor manufacture
#12 | 2016-08-02Method for fabricating multiple transistor devices on a substrate with varying threshold voltages
#13 | 2016-07-21Epitaxial Channel Transistors and Die With Diffusion Doped Channels
#14 | 2016-07-12CMOS structures and processes based on selective thinning
#15 | 2016-06-23Advanced transistors with punch through suppression
#16 | 2016-06-09Semiconductor structure with multiple transistors having various threshold voltages
#17 | 2016-05-19CMOS gate stack structures and processes
#18 | 2016-03-08CMOS gate stack structures and processes
#19 | 2015-11-26ADVANCED TRANSISTORS WITH THRESHOLD VOLTAGE SET DOPANT STRUCTURES
#20 | 2015-11-19Method for fabricating a transistor with reduced junction leakage current
#21 | 2015-10-08Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
#22 | 2015-08-18Semiconductor devices with dopant migration suppression and method of fabrication thereof
#23 | 2015-07-28Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
#24 | 2015-04-07Semiconductor structure with substitutional boron and method for fabrication thereof
#25 | 2015-03-05High uniformity screen and epitaxial layers for CMOS devices
#26 | 2015-02-24Electronic device with controlled threshold voltage
#27 | 2014-12-23Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
#28 | 2014-11-11Transistor having reduced junction leakage and methods of forming thereof
#29 | 2014-11-04Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom
#30 | 2014-09-25Transistor with threshold voltage set notch and method of fabrication thereof
#31 | 2014-08-05Monitoring and measurement of thin film layers
#32 | 2014-07-15Method for substrate preservation during transistor fabrication
#33 | 2014-06-19Source/drain extension control for advanced transistors
#34 | 2014-06-19Advanced transistors with punch through suppression
#35 | 2014-06-10Electronic device with controlled threshold voltage
#36 | 2014-05-27CMOS gate stack structures and processes
#37 | 2014-04-17Semiconductor structure with reduced junction leakage and method of fabrication thereof
#38 | 2014-03-27Deeply depleted MOS transistors having a screening layer and methods thereof
#39 | 2014-02-18Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
#40 | 2014-02-06Reducing or eliminating pre-amorphization in transistor manufacture
#41 | 2014-02-06Semiconductor structure and method of fabrication thereof with mixed metal types
#42 | 2014-01-16Source/drain extension control for advanced transistors
#43 | 2014-01-02Semiconductor structure with multiple transistors having various threshold voltages
#44 | 2013-12-24CMOS structures and processes based on selective thinning
#45 | 2013-12-12Low power semiconductor transistor structure and method of fabrication thereof
#46 | 2013-11-28Semiconductor structure with improved channel stack and method for fabrication thereof
#47 | 2013-10-29Reducing or eliminating pre-amorphization in transistor manufacture
#48 | 2013-07-18ADVANCED TRANSISTORS WITH PUNCH THROUGH SUPPRESSION
#49 | 2013-06-27Source/drain extension control for advanced transistors
#50 | 2012-09-06Semiconductor structure with improved channel stack and method for fabrication thereof
#51 | 2012-06-07Source/drain extension control for advanced transistors
#52 | 2012-04-05Method for minimizing defects in a semiconductor substrate due to ion implantation
#53 | 2011-12-22Semiconductor structure and method of fabrication thereof with mixed metal types
#54 | 2011-12-22Transistor with threshold voltage set notch and method of fabrication thereof
#55 | 2011-10-13Low power semiconductor transistor structure and method of fabrication thereof
#56 | 2011-05-26Advanced transistors with punch through suppression
#57 | 2011-04-07Advanced Transistors with Threshold Voltage Set Dopant Structures
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