Ramachandra Divakaruni

ACTIVE BRIDGE FOR CHIPLET AND MODULE INTER-COMMUNICATION

MULTI-CHIP HIGH MEMORY BANDWIDTH CONFIGURATION

NVM-BASED HIGH-CAPACITY NEURAL NETWORK INFERENCE ENGINE

Multiple chip bridge connector

Porous silicon relaxation medium for dislocation free CMOS devices

Third type of metal gate stack for CMOS devices

Fully depleted SOI device for reducing parasitic back gate capacitance

Porous silicon relaxation medium for dislocation free CMOS devices

FinFET with epitaxial source and drain regions and dielectric isolated channel region

Multiple-bit electrical fuses

Multiple-bit electrical fuses

FinFET vertical flash memory

Integrated strained stacked nanosheet FET

Fully depleted SOI device for reducing parasitic back gate capacitance

Vertical transistor including controlled gate length and a self-aligned junction

Porous silicon relaxation medium for dislocation free CMOS devices

Porous silicon relaxation medium for dislocation free CMOS devices

Method for forming an extremely thin silicon-on-insulator (ETSOI) device having reduced parasitic capacitance and contact resistance due to wrap-around structure of source/drain regions

Integrated strained stacked nanosheet FET

Fully depleted SOI device for reducing parasitic back gate capacitance

Vertical transistor including controlled gate length and a self-aligned junction

Integrated strained stacked nanosheet FET

Integrated strained stacked nanosheet FET

Stacked nanowire devices

Method for reduced parasitic capacitance and contact resistance in extremely thin silicon-on-insulator (ETSOI) devices due to wrap-around structure of source/drain regions

Forming nanotips

Integrated strained stacked nanosheet FET

Reduced parasitic capacitance and contact resistance in extremely thin silicon-on-insulator (ETSOI) devices due to wrap-around structure of source/drain regions

Stacked nanowire devices

Third type of metal gate stack for CMOS devices

Hybrid aspect ratio trapping

Partially dielectric isolated fin-shaped field effect transistor (FinFET)

FINFET CMOS with Si NFET and SiGe PFET

FinFET CMOS with Si NFET and SiGe PFET

FinFET with epitaxial source and drain regions and dielectric isolated channel region

Self-aligned punchthrough stop doping in bulk finFET by reflowing doped oxide

Vertical finfet with strained channel

Porous silicon relaxation medium for dislocation free CMOS devices

Porous silicon relaxation medium for dislocation free CMOS devices

Semiconductor fin isolation by a well trapping fin portion

Porous silicon relaxation medium for dislocation free CMOS devices

Partially dielectric isolated fin-shaped field effect transistor (FinFET)

LOCAL THINNING OF SEMICONDUCTOR FINS

Stacked nanowire devices

FinFET CMOS with Si NFET and SiGe PFET

Hybrid aspect ratio trapping

Y-FET with self-aligned punch-through-stop (PTS) doping

Multiple threshold voltage FinFETs

Finfet crosspoint flash memory

Self-aligned punchthrough stop doping in bulk finFET by reflowing doped oxide

Capacitor strap connection structure and fabrication method

FinFET with epitaxial source and drain regions and dielectric isolated channel region

FinFET vertical flash memory

Embedded flash memory fabricated in standard CMOS process with self-aligned contact

Trapping dislocations in high-mobility fins below isolation layer

Semiconductor structure having buried conductive elements

FinFET and fin-passive devices

Structure and method for effective device width adjustment in finFET devices using gate workfunction shift

Dielectric filler fins for planar topography in gate level

FinFET and fin-passive devices

FinFET with epitaxial source and drain regions and dielectric isolated channel region

Third type of metal gate stack for CMOS devices

Semiconductor structure having buried conductive elements

Local thinning of semiconductor fins

Finfet crosspoint flash memory

SUBSTRATE LOCAL INTERCONNECT INTEGRATION WITH FINFETS

Fin capacitor employing sidewall image transfer

Fin field effect transistor with dielectric isolation and anchored stressor elements

Dielectric filler fins for planar topography in gate level

Process for faciltiating fin isolation schemes

Intrinsic Channel Planar Field Effect Transistors Having Multiple Threshold Voltages

Fin transformation process and isolation structures facilitating different Fin isolation schemes

Semiconductor fin isolation by a well trapping fin portion

Methods and structures for protecting one area while processing another area on a chip

Strained finFET with an electrically isolated channel

Semiconductor fin isolation by a well trapping fin portion

Silicon-germanium fins and silicon fins on a bulk substrate

Strained finFET with an electrically isolated channel

Method and structure for forming a localized SOI finFET

REPLACEMENT GATE WITH AN INNER DIELECTRIC SPACER

ETCH STOP LAYER FORMATION IN METAL GATE PROCESS

Etch stop layer formation in metal gate process

REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT

Replacement Gate With Reduced Gate Leakage Current

Replacement metal gate structures providing independent control on work function and gate leakage current

Self-aligned contacts for high k/metal gate process flow

High capacitance trench capacitor

Source-drain extension formation in replacement metal gate transistor device

SOURCE-DRAIN EXTENSION FORMATION IN REPLACEMENT METAL GATE TRANSISTOR DEVICE

Integration of fin-based devices and ETSOI devices

Electrical fuse formed by replacement metal gate process

Integration of fin-based devices and ETSOI devices

Self-aligned contacts for high k/metal gate process flow

Method and structure for forming capacitors and memory devices on semiconductor-on-insulator (SOI) substrates

Replacement metal gate structures providing independent control on work function and gate leakage current

High capacitance trench capacitor

Electrically conductive path forming below barrier oxide layer and integrated circuit

Methods of fabricating P-I-N diodes, structures for P-I-N diodes and design structure for P-I-N diodes

Vertical metal-insulator-metal (MIM) capacitor using gate stack, gate spacer and contact via

Patterned strained semiconductor substrate and device