Inventor profile of:

Jong-Joo Lee

City:

Gyeonggi-do

Country:

South Korea

Published Applications:

24

Last publication date:

2025-08-14

Top Assignees for applications by Jong-Joo Lee

The entities that hold a legal rights for patent applications filed by inventor Lee Jong-Joo:

Recent patent applications by Lee Jong-Joo

Jong-Joo Lee from Gyeonggi-do, KR has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-08-14
US20250259693A1
Physics

MEMORY SYSTEM INCLUDING A SUB-CONTROLLER AND OPERATING METHOD OF THE SUB-CONTROLLER

#2 | 2024-11-28
US20240395292A1
Physics

STORAGE DEVICE BASED ON DAISY CHAIN TOPOLOGY

#3 | 2024-06-27
US20240212779A1
Physics

Memory system including a sub-controller and operating method of the sub-controller

#4 | 2023-04-13
US20230116063A1
Physics

Storage device based on daisy chain topology

#5 | 2022-12-08
US20220392559A1
Physics

Memory system including a sub-controller and operating method of the sub-controller

#6 | 2013-06-27
US20130161830A1
Electricity

Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the same

#7 | 2012-05-03
US20120104627A1
Electricity

Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the same

#8 | 2011-12-29
US20110316159A1
Electricity

Chip stack package

#9 | 2010-09-16
US20100230811A1
Electricity

Semiconductor device having a conductive bump

#10 | 2010-05-13
US20100117215A1
Electricity

Planar multi semiconductor chip package

#11 | 2009-08-27
US20090212414A1
Electricity

Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the same

#12 | 2009-04-30
US20090108469A1
Electricity

Chip stack package

#13 | 2009-03-12
US20090065950A1
Electricity

Stack chip and stack chip package having the same

#14 | 2008-11-27
US20080289177A1
Electricity

Method of fabricating a circuit board and semiconductor package.

#15 | 2008-09-04
US20080211081A1
Electricity

Planar multi semiconductor chip package and method of manufacturing the same

#16 | 2008-06-19
US20080142248A1
Electricity

Printed circuit board having coplanar LC balance

#17 | 2008-06-05
US20080128883A1
Electricity

High I/O semiconductor chip package and method of manufacturing the same

#18 | 2007-07-26
US20070170575A1
Electricity

Stack chip and stack chip package having the same

#19 | 2007-07-19
US20070164429A1
Electricity

Package board having internal terminal interconnection and semiconductor package employing the same

#20 | 2007-02-08
US20070029663A1
Electricity

Multilayered circuit substrate and semiconductor package structure using the same

#21 | 2006-10-05
US20060220215A1
Electricity

Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the same

#22 | 2006-06-29
US20060138648A1
Electricity

Semiconductor package module without a solder ball and method of manufacturing the semiconductor package module

#23 | 2006-06-22
US20060134833A1
Electricity

Packaged semiconductor die and manufacturing method thereof

#24 | 2005-09-15
US20050199993A1
Electricity

Semiconductor package having heat spreader and package stack using the same

InventorID:

307746 ⎘