Inventor profile of:

Gert Burbach

City:

Dresden

Country:

Germany

Published Applications:

12

Last publication date:

2012-02-02

Top Assignees for applications by Gert Burbach

The entities that hold a legal rights for patent applications filed by inventor Burbach Gert:

Recent patent applications by Burbach Gert

Gert Burbach from Dresden, DE has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2012-02-02
US20120025276A1
Electricity

Temperature monitoring in a semiconductor device by using a PN junction based on silicon/germanium materials

#2 | 2009-09-03
US20090218601A1
Electricity

TEMPERATURE MONITORING IN A SEMICONDUCTOR DEVICE BY USING AN PN JUNCTION BASED ON SILICON/GERMANIUM MATERIAL

#3 | 2007-11-01
US20070254444A1
Electricity

Semiconductor device having stressed etch stop layers of different intrinsic stress in combination with PN junctions of different design in different device regions

#4 | 2007-09-06
US20070207583A1
Electricity

METHOD OF FORMING A SEMICONDUCTOR STRUCTURE COMPRISING TRANSISTOR ELEMENTS WITH DIFFERENTLY STRESSED CHANNEL REGIONS

#5 | 2007-08-30
US20070202653A1
Electricity

Technique for forming a strained transistor by a late amorphization and disposable spacers

#6 | 2006-08-31
US20060194381A1
Electricity

Gate structure and a transistor having asymmetric spacer elements and methods of forming the same

#7 | 2006-03-02
US20060046400A1
Electricity

Method of forming a semiconductor structure comprising transistor elements with differently stressed channel regions

#8 | 2006-02-28
US10446974
-

Simultaneous formation of device and backside contacts on wafers having a buried insulator layer

#9 | 2006-02-02
US20060022197A1
Physics

Technique for evaluating local electrical characteristics in semiconductor devices

#10 | 2005-09-13
US10444191
-

Method of manufacturing a trench isolation structure for a semiconductor device with a different degree of corner rounding

#11 | 2005-06-14
US10629436
-

Diode structure for SOI circuits

#12 | 2005-05-12
US20050101120A1
Electricity

Method of forming local interconnect barrier layers

InventorID:

3086069 ⎘