Harm Peter Hofstee

SILICON CARRIER STRUCTURE AND METHOD OF FORMING SAME

Authenticating messages using cryptographic algorithm constants supplied to a storage-constrained target

Configurable interface controller

Silicon carrier structure and method of forming same

System and method for tracking messages between a processing unit and an external device

Supplying cryptographic algorithm constants to a storage-constrained target

Method and system for controlled distribution of application code and content data within a computer network

Method and system for controlled distribution of application code and content data within a computer network

Method for controlling rounding modes in single instruction multiple data (SIMD) floating-point units

Method and apparatus for cooperative software multitasking in a processor system with a partitioned register file

Processor Having Efficient Function Estimate Instructions

Multi-Chip Module With Third Dimension Interconnect

Dynamically partitioning processing across a plurality of heterogeneous processors

Integrated circuit chip with modular design

Systems and methods for time division multiplex multithreading

Method of logic circuit synthesis and design using a dynamic circuit library

Hiding memory latency

Non-Homogeneous Multi-Processor System With Shared Memory

Method of logic circuit synthesis and design using a dynamic circuit library

Method and System for Controlled Distribution of Application Code and Content Data Within a Computer Network

System and Method for Using a Plurality of Heterogeneous Processors in a Common Computer System

System and method for sharing memory by heterogeneous processors

System and Method for Executing Instructions Utilizing a Preferred Slot Alignment Mechanism

System for asynchronous DMA command completion notification wherein the DMA command comprising a tag belongs to a plurality of tag groups

Computer architecture and software cells for broadband networks

Computer architecture and software cells for broadband networks

Clock-gating through data independent logic

System and method asynchronous DMA command completion notification by accessing register via attached processing unit to determine progress of DMA command

Lowered PU power usage method and apparatus

Modular design method and apparatus

Random number generator

Method of functionality testing for a ring oscillator

Method, apparatus and computer program product for write data transfer

Processor having efficient function estimate instructions

Oscillator array with row and column control

Systems and methods for adaptively mapping an instruction cache

Memory management for real-time applications

Non-homogeneous multi-processor system with shared memory

Memory with combined line and word access

Systems and methods for time division multiplex multithreading

SIMD-RISC processor module

Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units

Ring-topology based multiprocessor data access bus

System and method for hiding memory latency

Hierarchical management for multiprocessor system with real-time attributes

Hierarchical management for multiprocessor system

Microprocessor chip simultaneous switching current reduction method and apparatus

Communications bus with redundant signal paths and method for compensating for signal path errors in a communications bus

Memory management in multiprocessor system

System and method for using a plurality of heterogeneous processors in a common computer system

Method and system for maintaining coherency in a multiprocessor system by broadcasting TLB invalidated entry instructions

Random carry-in for floating-point operations

Efficient function interpolation using SIMD vector permute functionality

Unidirectional message masking and validation system and method

SIMD-RISC microprocessor architecture

Method and apparatus for evaluating results of multiple software tools

Multi-chip module with third dimension interconnect

Methods for supplying cryptographic algorithm constants to a storage-constrained target

Symmetric multi-processing system utilizing a DMAC to allow address translation for attached processors

System and method for sharing memory by heterogeneous processors

System and method for a configurable interface controller

Removeable ESD for improving I/O pin bandwidth

Dynamically partitioning processing across plurality of heterogeneous processors

Method and apparatus for coherent memory structure of heterogeneous processor systems

System and method for selecting and using a signal processor in a multiprocessor system to operate as a security for encryption/decryption of data

Software-controlled cache set management

Software-controlled cache set management with software-generated class identifiers

Random carry-in for floating-point operations

Reduction of interrupts in remote procedure calls

Security architecture for system on chip

System and method for encrypting and verifying messages using three-phase encryption

SIMD datapath coupled to scalar/vector/address/conditional data register file with selective subpath scalar processing mode