Los Gatos, California
United States
45
2025-03-06
The entities that hold a legal rights for patent applications filed by inventor YIP Aaron:
Aaron YIP from Los Gatos, US has applied for patents for these inventions. The list has both pending applications and granted patents:
REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICES
#2 | 2025-01-30MEMORY DEVICES INCLUDING STAIRCASE STRUCTURES, AND RELATED ELECTRONIC SYSTEMS
#3 | 2025-01-303D MEMORY DEVICE INCLUDING SHARED SELECT GATE CONNECTIONS BETWEEN MEMORY BLOCKS
#4 | 2024-02-22WAFER-ON-WAFER MEMORY DEVICE ARCHITECTURES
#5 | 2023-12-283D memory device including shared select gate connections between memory blocks
#6 | 2023-11-09Reducing programming disturbance in memory devices
#7 | 2022-12-01Devices including stair step structures, and related memory devices and electronic systems
#8 | 2022-11-10Reducing programming disturbance in memory devices
#9 | 2022-02-173D memory device including shared select gate connections between memory blocks
#10 | 2021-09-16Reducing programming disturbance in memory devices
#11 | 2021-06-24Memory device including data lines on multiple device levels
#12 | 2021-05-20Methods of forming memory devices including stair step structures
#13 | 2021-01-07Memory block select circuitry including voltage bootstrapping control
#14 | 2020-11-24Microelectronic devices including staircase structures, and related memory devices and electronic systems
#15 | 2020-11-123D memory device including shared select gate connections between memory blocks
#16 | 2020-10-08Reducing programming disturbance in memory devices
#17 | 2019-12-05Sense flags in a memory device
#18 | 2019-09-26Memory block select circuitry including voltage bootstrapping control
#19 | 2019-08-22Memory devices including stair step or tiered structures and related methods
#20 | 2019-07-18Apparatuses and methods using dummy cells programmed to different states
#21 | 2019-05-163D memory device including shared select gate connections between memory blocks
#22 | 2019-03-14Memories having select devices between access lines and in memory cells
#23 | 2019-01-10Apparatuses and methods using dummy cells programmed to different states
#24 | 2018-12-27Sense flags in a memory device
#25 | 2018-11-08Memories having select devices between access lines and in memory cells
#26 | 2018-09-13Method and apparatus for shielded read to reduce parasitic capacitive coupling
#27 | 2018-07-19Methods of forming conductive structures including stair step or tiered structures having conductive portions
#28 | 2018-01-09Performing read operations on a memory device
#29 | 2017-11-09Memories having select devices between access lines and in memory cells formed of a same type of circuit element
#30 | 2017-10-05Apparatuses and methods using dummy cells programmed to different states
#31 | 2017-09-14Conductive structures, systems and devices including conductive structures and related methods
#32 | 2017-03-16Sense operation flags in a memory device
#33 | 2016-11-24Apparatuses and methods using dummy cells programmed to different states
#34 | 2016-04-14Apparatuses and methods using dummy cells programmed to different states
#35 | 2016-01-28Semiconductor devices including stair step structures, and related methods
#36 | 2015-12-17Sense operation flags in a memory device
#37 | 2015-04-16Systems with memory segmentation and systems with biasing lines to receive same voltages during accessing
#38 | 2015-01-01Semiconductor devices including stair step structures, and related methods
#39 | 2014-03-06Diode segmentation in memory
#40 | 2014-01-30Methods and devices for memory reads with precharged data lines
#41 | 2013-07-04Sharing local control lines across multiple planes in a memory device
#42 | 2013-06-27Multi-pass programming in a memory device
#43 | 2012-10-11Methods and devices for memory reads with precharged data lines
#44 | 2012-05-10Sense operation flags in a memory device
#45 | 2012-03-29Access line management in a memory device
309916 ⎘