Wayne E. Werner

Memory device with phase distribution circuit for controlling relative durations of precharge and active phases

Memory Cell Using Leakage Current Storage Mechanism

High-reliability memory

Secure random number generator

Optimization of circuits having repeatable circuit instances

Accessing memory cells in a memory circuit

Integrated circuit self-monitored burn-in

Tracking circuit for reducing faults in a memory

Method and apparatus for increasing yield in a memory device

Systematic error correction for multi-level flash memory

Memory device with reduced buffer current during power-down mode

Method and apparatus for testing a memory device

Word line driver circuit with reduced leakage

Sense amplifier with redundancy

Memory device with error correction capability and efficient partial word write operation

Memory circuit having reduced power consumption

Multiple-level memory with analog read

Dynamic random access memory with low-power refresh

Reduced leakage driver circuit and memory device employing same

Method and apparatus for idle cycle refresh request in DRAM

Dual-port memory

Memory device with error correction capability and preemptive partial word write operation

Memory cell for content-addressable memory

Memory device with error correction based on automatic logic inversion

Integrated circuit having a memory with process-voltage-temperature control

Accelerated searching for content-addressable memory

Accelerated single-ended sensing for a memory circuit

Decoding techniques for read-only memory

Layout techniques for memory circuitry