Jiangqi He

Self referencing pin

Substrate With Raised Edge Pads

Forming compliant contact pads for semiconductor packages

Multi-chip assembly with optically coupled die

Integrated capacitors in package-level structures, processes of making same, and systems containing same

Multi-chip assembly with optically coupled die

Forming compliant contact pads for semiconductor packages

Package Including a Microprocessor & Fourth Level Cache

Reducing input capacitance of high speed integrated circuits

Package level integration of antenna and RF front-end module

Double side stacked die package

Integrated circuit package with chip-side signal connections

Substrate with lossy material insert

I/O Architecture for integrated circuit package

Dual-chip integrated heat spreader assembly, packages containing same, and systems containing same

Dual heat spreader panel assembly method for bumpless die-attach packages, packages containing same, and systems containing same

Electronic assembly with stacked IC's using two or more different connection technologies and methods of manufacture

Chip-to-chip optical interconnect

INTEGRATED INDUCTORS AND COMPLIANT INTERCONNECTS FOR SEMICONDUCTOR PACKAGING

Transmission line impedance matching

Integrated capacitors in package-level structures, processes of making same, and systems containing same

Edge interconnects for die stacking

Substrate with raised edge pads

Data signal interconnection with reduced crosstalk

Packaged spiral inductor structures, processes of making same, and systems containing same

Dual die package with high-speed interconnect

Complementary inductor structures

Plating bar design for high speed package design

Integrated circuit package to provide high-bandwidth communication among multiple dice

Forming compliant contact pads for semiconductor packages

Multi-chip assembly with optically coupled die

Integrated micro-channels for 3D through silicon architectures

Reducing parasitic mutual capacitances

IC package with signal land pads

Transmission line impedance matching

Methods of forming in package integrated capacitors and structures formed thereby

Methods of forming in package integrated capacitors and structures formed thereby

Array capacitor apparatuses to filter input/output signal

Integrated inductors and compliant interconnects for semiconductor packaging

Package integrated one-quarter wavelength and three-quarter wavelength balun

Transmission line impedance matching

Extended thin film capacitor (TFC)

Extended thin film capacitor (TFC)

Reference slots for signal traces

Integrated circuit package with chip-side signal connections

Vertical capacitor apparatus, systems, and methods

Multilayer inductor with shielding plane

Differential signal traces coupled with high permittivity material

Floating trace on signal layer

Vertical capacitor apparatus, systems, and methods

Silicon building blocks in integrated circuit packaging