David James Williamson

Decoding conditional program instructions

Set of system configuration registers having shadow register

Renaming wide register source operand with plural short register source operands for select instructions to detect dependency fast with existing mechanism

Method and apparatus with data storage protocols for maintaining consistencies in parallel translation lookaside buffers

Result path sharing between a plurality of execution units within a processor

Branch prediction in a data processing system utilizing a cache of previous static predictions

Preventing loss of traced information in a data processing apparatus

Performance of a data processing apparatus

Instruction queues in pipelined processors

Branch prediction apparatus for repurposing a branch to instruction set as a non-predicted branch

Result bypassing to override a data hazard within a superscalar processor

Data processing apparatus and method for executing a sequence of instructions including a multiple iteration instruction

Indicating storage locations within caches

Provision of debug via a separate ring bus in a data processing apparatus

Performance of a data processing apparatus

Tracing out-of-order data

Tracing multiple data access instructions

Tracing multiple data access instructions

Apparatus and method for facilitating debugging of sequences of processing instructions using context identifier comparison