Mahender Kumar

Methods to control fin tip placement

Threshold voltage and well implantation method for semiconductor devices

Self-protected electrostatic discharge field effect transistor (SPESDFET), an integrated circuit incorporating the SPESDFET as an input/output (I/O) pad driver and associated methods of forming the SPESDFET and the integrated circuit

EDRAM including metal plates

Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof

Methods for forming high performance gates and structures thereof

Structures, fabrication methods, design structures for strained fin field effect transistors (FinFets)

FINFET DEVICES FROM BULK SEMICONDUCTOR AND METHODS FOR MANUFACTURING THE SAME

Method and structure for forming multiple self-aligned gate stacks for logic devices

Structure and method for manufacturing device with ultra thin SOI at the tip of a V-shape channel

Dual metal gate finFETs with single or dual high-K gate dielectric

CONTACT FORMING IN TWO PORTIONS AND CONTACT SO FORMED

Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation

Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof

PERFORMANCE ENHANCEMENT ON BOTH NMOSFET AND PMOSFET USING SELF-ALIGNED DUAL STRESSED FILMS

ULTRA-THIN SOI VERTICAL BIPOLAR TRANSISTORS WITH AN INVERSION COLLECTOR ON THIN-BURIED OXIDE (BOX) FOR LOW SUBSTRATE-BIAS OPERATION AND METHODS THEREOF

Field effect device including inverted V shaped channel region and method for fabrication thereof

METAL GATE MOSFET BY FULL SEMICONDUCTOR METAL ALLOY CONVERSION

Metal gate MOSFET by full semiconductor metal alloy conversion

Method of fabricating a vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness

STI formation in semiconductor device including SOI and bulk silicon regions

Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation

STI formation in semiconductor device including SOI and bulk silicon regions

Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof

Method for deep trench etching through a buried insulator layer