Sunnyvale, California
United States
14
2009-07-16
11
2011-10-04
These are the the leading inventors for applications assigned to ADVANCED MICRO DEVICES, INC. (AMD):
ADVANCED MICRO DEVICES, INC. (AMD) based in Sunnyvale, US has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:
Metal gate stack and semiconductor gate stack for CMOS devices
#2 | 2009-06-18 ✅ Patent 8,053,306 granted on 2011-11-08PFET with tailored dielectric and related methods and integrated circuit
#3 | 2009-06-18METHOD AND STRUCTURE FOR SEMICONDUCTOR DEVICES WITH SILICON-GERMANIUM DEPOSITS
#4 | 2009-06-18 ✅ Patent 7,985,928 granted on 2011-07-26Gap free anchored conductor and dielectric structure and method for fabrication thereof
#5 | 2009-06-11 ✅ Patent 7,671,362 granted on 2010-03-02Test structure for determining optimal seed and liner layer thicknesses for dual damascene processing
#6 | 2009-06-04 ✅ Patent 7,790,541 granted on 2010-09-07Method and structure for forming multiple self-aligned gate stacks for logic devices
#7 | 2008-12-04 ✅ Patent 7,512,506 granted on 2009-03-31IC chip stress testing
#8 | 2008-04-17 ✅ Patent 7,820,501 granted on 2010-10-26Decoder for a stationary switch machine
#9 | 2008-04-10 ✅ Patent 7,494,918 granted on 2009-02-24Semiconductor structures including multiple crystallographic orientations and methods for fabrication thereof
#10 | 2007-05-24 ✅ Patent 7,659,172 granted on 2010-02-09Structure and method for reducing miller capacitance in field effect transistors
#11 | 2007-03-29PREVENTING DAMAGE TO INTERLEVEL DIELECTRIC
#12 | 2007-03-01RETAINING RING STRUCTURE FOR ENHANCED REMOVAL RATE DURING FIXED ABRASIVE CHEMICAL MECHANICAL POLISHING
#13 | 2007-01-25 ✅ Patent 7,244,644 granted on 2007-07-17Undercut and residual spacer prevention for dual stressed layers
#14 | 2007-01-11 ✅ Patent 7,485,521 granted on 2009-02-03Self-aligned dual stressed layers for NFET and PFET
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