Scott LUNING

STRAINED MOS DEVICE AND METHODS FOR ITS FABRICATION

Semiconductor device with stressed fin sections

METAL OXIDE SEMICONDUCTOR TRANSISTOR WITH REDUCED GATE HEIGHT, AND RELATED FABRICATION METHODS

Semiconductor device with stressed fin sections, and related fabrication methods

Embedded silicon germanium source drain structure with reduced silicide encroachment and contact resistance and enhanced channel mobility

Methods for fabricating non-planar semiconductor devices having stress memory

MOSFET with asymmetrical extension implant

Methods for fabricating FinFET semiconductor devices using L-shaped spacers

FINFET STRUCTURES WITH FINS HAVING STRESS-INDUCING CAPS AND METHODS FOR FABRICATING THE SAME

FinFET structures with stress-inducing source/drain-forming spacers and methods for fabricating the same

SEMICONDUCTOR TRANSISTOR DEVICE WITH IMPROVED ISOLATION ARRANGEMENT, AND RELATED FABRICATION METHODS

MOSFET with asymmetrical extension implant

Metal oxide semiconductor transistor with reduced gate height, and related fabrication methods

Stressed field effect transistor and methods for its fabrication

Stacking fault reduction in epitaxially grown silicon

Methods for fabricating a stress enhanced semiconductor device having narrow pitch and wide pitch transistors

STRESS ENHANCED MOS TRANSISTOR AND METHODS FOR ITS FABRICATION

Stressed field effect transistor and methods for its fabrication

Strained MOS device and methods for its fabrication

Stacking fault reduction in epitaxially grown silicon

Methods for manufacturing integrated circuits

Method of forming an epitaxial layer for raised drain and source regions by removing surface defects of the initial crystal surface

Integrated circuit and method for its manufacture

Advanced technique for forming a transistor having raised drain and source regions