Casey Scott

Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions

Transistor with embedded Si/Ge material having enhanced across-substrate uniformity

Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions

HIGH-K ETCH STOP LAYER OF REDUCED THICKNESS FOR PATTERNING A DIELECTRIC MATERIAL DURING FABRICATION OF TRANSISTORS

Transistor device comprising an asymmetric embedded semiconductor alloy

Transistor with embedded SI/GE material having enhanced across-substrate uniformity

Cold temperature control in a semiconductor device

In situ formed drain and source regions in a silicon/germanium containing transistor device

Reduction of memory instability by local adaptation of re-crystallization conditions in a cache area of a semiconductor device

Temperature monitoring in a semiconductor device by thermocouples distributed in the contact structure

Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions

Method for creating tensile strain by selectively applying stress memorization techniques to NMOS transistors

COMPENSATION OF OPERATING TIME RELATED DEGRADATION OF OPERATING SPEED BY ADAPTING THE SUPPLY VOLTAGE

TECHNIQUE FOR ENHANCING DOPANT ACTIVATION BY USING MULTIPLE SEQUENTIAL ADVANCED LASER/FLASH ANNEAL PROCESSES

SOI transistor having drain and source regions of reduced length and a stressed dielectric material adjacent thereto

Method for forming silicon/germanium containing drain/source regions in transistors with reduced silicon/germanium loss