Dresden
Germany
19
2012-09-06
The entities that hold a legal rights for patent applications filed by inventor Gehring Andreas:
Andreas Gehring from Dresden, DE has applied for patents for these inventions. The list has both pending applications and granted patents:
Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions
#2 | 2011-07-28SOI device having a substrate diode with process tolerant configuration and method of forming the SOI device
#3 | 2010-09-23Reducing transistor junction capacitance by recessing drain and source regions
#4 | 2010-06-24Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions
#5 | 2009-12-03In situ formed drain and source regions in a silicon/germanium containing transistor device
#6 | 2009-10-01Method for creating tensile strain by applying stress memorization techniques at close proximity to the gate electrode
#7 | 2009-07-02Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions
#8 | 2009-06-04Method for creating tensile strain by selectively applying stress memorization techniques to NMOS transistors
#9 | 2009-04-30INCREASING ETCH SELECTIVITY DURING THE PATTERNING OF A CONTACT STRUCTURE OF A SEMICONDUCTOR DEVICE
#10 | 2009-02-05Method of forming a semiconductor structure comprising an implantation of ions of a non-doping element
#11 | 2009-01-01Reducing transistor junction capacitance by recessing drain and source regions
#12 | 2008-10-30SOI device having a substrate diode with process tolerant configuration and method of forming the SOI device
#13 | 2008-10-02Method for creating tensile strain by repeatedly applied stress memorization techniques
#14 | 2008-08-28Method for differential spacer removal by wet chemical etch process and device with differential spacer structure
#15 | 2008-08-28Semiconductor device having a strained semiconductor alloy concentration profile
#16 | 2008-07-31Method for forming silicon/germanium containing drain/source regions in transistors with reduced silicon/germanium loss
#17 | 2008-05-01Method of forming a semiconductor structure comprising a field effect transistor having a stressed channel region
#18 | 2008-04-03Method for reducing crystal defects in transistors with re-grown shallow junctions by appropriately selecting crystalline orientations
#19 | 2008-01-03Transistor having a channel with biaxial strain induced by silicon/germanium in the gate electrode
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