William C. Hasenplaugh

Processors, methods, systems, and instructions to load multiple data elements to destination storage locations other than packed data registers

Processors, methods, systems, and instructions to load multiple data elements to destination storage locations other than packed data registers

Low energy consumption mantissa multiplication for floating point multiply-add operations

Address range priority mechanism

Multicast tree-based data distribution in distributed shared cache

Hardware apparatuses and methods to control cache line coherency

Hardware compilation and/or translation with fault detection and roll back functionality

Scalable multi-layer 2D-mesh routers

Retrieval of previously accessed data in a multi-core processor

High bandwidth full-block write commands

Distributed power management for multi-core processors

Update mask for handling interaction between fills and updates

Domain state

Signature based hit-predicting cache

DATA CONTROL USING LAST ACCESSOR INFORMATION

Address range priority mechanism

Short circuit of probes in a chain

Efficient support of sparse data structure access

Hardware compilation and/or translation with fault detection and roll back functionality

Method and apparatus for optimizing the usage of cache memories

Probe speculative address file

CROSS-FEEDBACK PHASE-LOCKED LOOP FOR DISTRIBUTED CLOCKING SYSTEMS

Cache spill management techniques using cache spill prediction