Inventor profile of:

Xiaomeng Chen

City:

Poughkeepsie, New York

Country:

United States

Published Applications:

20

Last publication date:

2012-11-22

Top Assignees for applications by Xiaomeng Chen

The entities that hold a legal rights for patent applications filed by inventor Chen Xiaomeng:

Recent patent applications by Chen Xiaomeng

Xiaomeng Chen from Poughkeepsie, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2012-11-22
US20120292668A1
Electricity

CMOS devices incorporating hybrid orientation technology (HOT) with embedded connectors

#2 | 2010-11-04
US20100279508A1
Electricity

Method for reducing amine based contaminants

#3 | 2010-08-05
US20100197118A1
Electricity

Multiple crystallographic orientation semiconductor structures

#4 | 2010-01-14
US20100006926A1
Electricity

Methods for forming high performance gates and structures thereof

#5 | 2009-12-31
US20090321828A1
Electricity

Structures, fabrication methods, design structures for strained fin field effect transistors (FinFets)

#6 | 2009-12-31
US20090321794A1
Electricity

CMOS devices incorporating hybrid orientation technology (HOT) with embedded connectors

#7 | 2009-11-19
US20090283836A1
Electricity

CMOS STRUCTURE INCLUDING PROTECTIVE SPACERS AND METHOD OF FORMING THEREOF

#8 | 2009-10-15
US20090256207A1
Electricity

FINFET DEVICES FROM BULK SEMICONDUCTOR AND METHODS FOR MANUFACTURING THE SAME

#9 | 2009-04-30
US20090108302A1
Electricity

Multiple crystallographic orientation semiconductor structures

#10 | 2008-09-18
US20080224255A1
Electricity

SUBGROUND RULE STI FILL FOR HOT STRUCTURE

#11 | 2008-08-07
US20080185592A1
Electricity

Semiconductor substrate with multiple crystallographic orientations

#12 | 2008-07-17
US20080169528A1
Electricity

Subground rule STI fill for hot structure

#13 | 2008-07-03
US20080157200A1
Electricity

STRESS LINER SURROUNDED FACETLESS EMBEDDED STRESSOR MOSFET

#14 | 2008-05-29
US20080121931A1
Electricity

Semiconductor structure having undercut-gate-oxide gate stack enclosed by protective barrier material

#15 | 2008-04-10
US20080083952A1
Electricity

Semiconductor structures including multiple crystallographic orientations and methods for fabrication thereof

#16 | 2008-03-13
US20080064160A1
Electricity

CMOS devices incorporating hybrid orientation technology (HOT) with embedded connectors

#17 | 2008-03-06
US20080057673A1
Electricity

Method of making a semiconductor structure

#18 | 2007-02-01
US20070026683A1
Electricity

Method for reducing amine based contaminants

#19 | 2006-12-26
US10605926
-

Method for reducing amine based contaminants

#20 | 2005-05-05
US20050095841A1
Electricity

Semiconductor structure having reduced amine-based contaminants

InventorID:

3297907 ⎘