San Jose, California
United States
166
2025-11-13
The entities that hold a legal rights for patent applications filed by inventor Ramkumar Krishnaswamy:
Krishnaswamy Ramkumar from San Jose, US has applied for patents for these inventions. The list has both pending applications and granted patents:
METHODS OF EQUALIZING GATE HEIGHTS IN EMBEDDED NON-VOLATILE MEMORY ON HKMG TECHNOLOGY
#2 | 2025-06-05METHOD OF FORMING OXIDE-NITRIDE-OXIDE STACK OF NON-VOLATILE MEMORY AND INTEGRATION TO CMOS PROCESS FLOW
#3 | 2025-03-11Methods of equalizing gate heights in embedded non-volatile memory on HKMG technology
#4 | 2024-10-03MEMORY TRANSISTOR WITH MULTIPLE CHARGE STORING LAYERS AND A HIGH WORK FUNCTION GATE ELECTRODE
#5 | 2024-07-11Oxide-Nitride-Oxide Stack Having Multiple Oxynitride Layers
#6 | 2024-03-28Method of forming oxide-nitride-oxide stack of non-volatile memory and integration to CMOS process flow
#7 | 2023-06-29Method of ono integration into logic CMOS flow
#8 | 2023-03-16Method of Integrating SONOS into HKMG Flow
#9 | 2023-03-09SONOS ONO STACK SCALING
#10 | 2023-01-26Memory transistor with multiple charge storing layers and a high work function gate electrode
#11 | 2023-01-19Oxide-nitride-oxide stack having multiple oxynitride layers
#12 | 2022-11-10Silicon-oxide-nitride-oxide-silicon multi-level non-volatile memory device and methods of fabrication thereof
#13 | 2022-09-08Silicon-oxide-nitride-oxide-silicon based multi-level non-volatile memory device and methods of operation thereof
#14 | 2022-06-02SONOS STACK WITH SPLIT NITRIDE MEMORY LAYER
#15 | 2022-03-24Oxide-nitride-oxide stack having multiple oxynitride layers
#16 | 2022-01-06Memory transistor with multiple charge storing layers and a high work function gate electrode
#17 | 2021-11-11Silicon-oxide-nitride-oxide-silicon based multi-level non-volatile memory device and methods of operation thereof
#18 | 2021-08-12OXIDE-NITRIDE-OXIDE STACK HAVING MULTIPLE OXYNITRIDE LAYERS
#19 | 2021-07-15Memory transistor with multiple charge storing layers and a high work function gate electrode
#20 | 2021-06-24Method of ono integration into logic CMOS flow
#21 | 2021-05-27Silicon-oxide-nitride-oxide-silicon multi-level non-volatile memory device and methods of fabrication thereof
#22 | 2021-05-27Silicon-oxide-nitride-oxide-silicon based multi level non-volatile memory device and methods of operation thereof
#23 | 2021-04-08SONOS ONO STACK SCALING
#24 | 2021-03-11Sonos stack with split nitride memory layer
#25 | 2021-03-11EMBEDDED SONOS WITH TRIPLE GATE OXIDE AND MANUFACTURING METHOD OF THE SAME
#26 | 2020-11-05Embedded SONOS and high voltage select gate with a high-K metal gate and manufacturing methods of the same
#27 | 2020-09-24NONVOLATILE CHARGE TRAP MEMORY DEVICE HAVING A HIGH DIELECTRIC CONSTANT BLOCKING REGION
#28 | 2020-09-10RADICAL OXIDATION PROCESS FOR FABRICATING A NONVOLATILE CHARGE TRAP MEMORY DEVICE
#29 | 2020-06-30Method of ONO integration into logic CMOS flow
#30 | 2020-05-21OXIDE FORMATION IN A PLASMA PROCESS
#31 | 2020-05-14Flash memory device and method
#32 | 2020-05-07Oxide-nitride-oxide stack having multiple oxynitride layers
#33 | 2020-04-09Method of ONO Stack Formation
#34 | 2020-02-13BIAS SCHEME FOR WORD PROGRAMMING IN NON-VOLATILE MEMORY AND INHIBIT DISTURB REDUCTION
#35 | 2020-01-16Method of integrating a charge-trapping gate stack into a CMOS flow
#36 | 2019-12-05Embedded sonos with a high-K metal gate and manufacturing methods of the same
#37 | 2019-10-17NONVOLATILE CHARGE TRAP MEMORY DEVICE HAVING A DEUTERATED LAYER IN A MULTI-LAYER CHARGE-TRAPPING REGION
#38 | 2019-06-27SONOS stack with split nitride memory layer
#39 | 2019-05-23Method of ONO stack formation
#40 | 2019-05-16Bias scheme for word programming in non-volatile memory and inhibit disturb reduction
#41 | 2019-04-04EMBEDDED SONOS WITH A HIGH-K METAL GATE AND MANUFACTURING METHODS OF THE SAME
#42 | 2019-03-21Oxide formation in a plasma process
#43 | 2019-03-21Embedded sonos with triple gate oxide and manufacturing method of the same
#44 | 2019-02-28Method of integrating a charge-trapping gate stack into a CMOS flow
#45 | 2018-12-20Oxide-nitride-oxide stack having multiple oxynitride layers
#46 | 2018-12-20Oxide-nitride-oxide stack having multiple oxynitride layers
#47 | 2018-12-06Radical oxidation process for fabricating a nonvolatile charge trap memory device
#48 | 2018-12-06SONOS ONO stack scaling
#49 | 2018-08-28Embedded SONOS with triple gate oxide and manufacturing method of the same
#50 | 2018-06-14Integration of a memory transistor into High-k, metal gate CMOS process flow
#51 | 2018-06-07Memory transistor with multiple charge storing layers and a high work function gate electrode
#52 | 2018-03-22Method of ONO stack formation
#53 | 2018-03-06Integration of a memory transistor into high-k, metal gate CMOS process flow
#54 | 2018-02-22SONOS stack with split nitride memory layer
#55 | 2018-02-08Complementary SONOS integration into CMOS flow
#56 | 2017-12-07Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
#57 | 2017-11-21Method of integration of ONO stack formation into thick gate oxide CMOS flow
#58 | 2017-10-17Method of ONO stack formation
#59 | 2017-09-28Integration of a memory transistor into high-k, metal gate CMOS process flow
#60 | 2017-09-14Memory device with multi-layer channel and charge trapping layer
#61 | 2017-09-14Embedded SONOS based memory cells
#62 | 2017-08-01Integration of a memory transistor into high-k, metal gate CMOS process flow
#63 | 2017-06-29Memory transistor with multiple charge storing layers and a high work function gate electrode
#64 | 2017-03-30Nonvolatile charge trap memory device having a high dielectric constant blocking region
#65 | 2017-03-30Memory transistor with multiple charge storing layers and a high work function gate electrode
#66 | 2017-03-23Method of fabricating a charge-trapping gate stack using a CMOS process flow
#67 | 2017-01-05Oxide formation in a plasma process
#68 | 2016-11-22Method of manufacturing for memory transistor with multiple charge storing layers and a high work function gate electrode
#69 | 2016-10-20Oxide-nitride-oxide stack having multiple oxynitride layers
#70 | 2016-10-20Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
#71 | 2016-10-13SONOS ONO stack scaling
#72 | 2016-10-13Oxide-nitride-oxide stack having multiple oxynitride layers
#73 | 2016-10-04Oxide formation in a plasma process
#74 | 2016-09-08Embedded SONOS based memory cells
#75 | 2016-08-02Oxide formation in a plasma process
#76 | 2016-07-14Complimentary SONOS integration into CMOS flow
#77 | 2016-05-31Oxide-nitride-oxide stack having multiple oxynitride layers
#78 | 2016-05-24Nitridation oxidation of tunneling layer for improved SONOS speed and retention
#79 | 2016-05-19SONOS stack with split nitride memory layer
#80 | 2016-04-07Method of integrating a charge-trapping gate stack into a CMOS flow
#81 | 2016-01-07Method of fabricating a charge-trapping gate stack using a CMOS process flow
#82 | 2015-12-22Method of ONO stack formation
#83 | 2015-10-08Methods to integrate SONOS into CMOS flow
#84 | 2015-07-02Radical oxidation process for fabricating a nonvolatile charge trap memory device
#85 | 2015-06-18COMPLEMENTARY SONOS INTEGRATION INTO CMOS FLOW
#86 | 2015-06-18Non-volatile memory and method of operating the same
#87 | 2015-05-05Simultaneously forming a dielectric layer in MOS and ONO device regions
#88 | 2015-03-31Method of fabricating a charge-trapping gate stack using a CMOS process flow
#89 | 2015-03-31Deuterated film encapsulation of nonvolatile charge trap memory device
#90 | 2015-03-31Method of fabricating a nonvolatile charge trap memory device
#91 | 2015-02-12Embedded SONOS based memory cells
#92 | 2015-02-12Memory transistor with multiple charge storing layers and a high work function gate electrode
#93 | 2015-01-01Methods of fabricating an F-RAM
#94 | 2014-12-25SONOS stack with split nitride memory layer
#95 | 2014-12-23Methods to integrate SONOS into CMOS flow
#96 | 2014-11-11Integration of a memory transistor into high-K, metal gate CMOS process flow
#97 | 2014-10-14Memory transistor with multiple charge storing layers and a high work function gate electrode
#98 | 2014-09-25Oxide-nitride-oxide stack having multiple oxynitride layers
#99 | 2014-09-18Memory transistor with multiple charge storing layers and a high work function gate electrode
#100 | 2014-09-18Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
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