Chappaqua, New York
United States
505
2021-07-22
The entities that hold a legal rights for patent applications filed by inventor Gschwind Michael K.:
Michael K. Gschwind from Chappaqua, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Portions of configuration state registers in-memory
#2 | 2020-05-21Controlling a rate of prefetching based on bus bandwidth
#3 | 2020-04-23SHARING SNAPSHOTS BETWEEN RESTORATION AND RECOVERY
#4 | 2020-04-16Automatic pinning of units of memory
#5 | 2020-02-27Determining the effectiveness of prefetch instructions
#6 | 2020-02-06Initializing a data structure for use in predicting table of contents pointer values
#7 | 2020-01-30Configurable code fingerprint
#8 | 2020-01-30Predicting a table of contents pointer value responsive to branching to a subroutine
#9 | 2020-01-09Automatic pinning of units of memory
#10 | 2020-01-02Determining and predicting derived values
#11 | 2020-01-02Code-specific affiliated register prediction
#12 | 2020-01-02Context information based on type of routine being called
#13 | 2019-12-12Set table of contents (TOC) register instruction
#14 | 2019-12-12Protecting in-memory configuration state registers
#15 | 2019-12-05Context switch by changing memory pointers
#16 | 2019-11-14Portions of configuration state registers in-memory
#17 | 2019-11-07Table of contents cache entry having a pointer for a range of addresses
#18 | 2019-11-07Table of contents cache entry having a pointer for a range of addresses
#19 | 2019-11-07Architectural mode configuration
#20 | 2019-11-07Architectural mode configuration
#21 | 2019-10-31Delaying branch prediction updates specified by a suspend branch prediction instruction until after a transaction is completed
#22 | 2019-10-31Effectiveness and prioritization of prefetches
#23 | 2019-10-24Architecturally paired spill/reload multiple instructions for suppressing a snapshot latest value determination
#24 | 2019-10-24Instructions to count a number of contiguous register elements having specific values in a selected location
#25 | 2019-10-24Instructions to count a number of contiguous register elements having specific values in a selected location
#26 | 2019-10-17Debugging of prefixed code
#27 | 2019-10-03Effectiveness and prioritization of prefetches
#28 | 2019-09-19Facilitating access to memory locality domain information
#29 | 2019-09-19Locality domain-based memory pools for virtualized computing environment
#30 | 2019-09-12Simultaneously capturing status information for multiple operating modes
#31 | 2019-09-05Indicator-based prioritization of transactions
#32 | 2019-08-29Compiler controls for program regions
#33 | 2019-08-22Selecting processing based on expected value of selected character
#34 | 2019-08-22Selecting processing based on expected value of selected character
#35 | 2019-08-01Suppressing branch prediction on a repeated execution of an aborted transaction
#36 | 2019-07-25Suppressing branch prediction updates until forward progress is made in execution of a previously aborted transaction
#37 | 2019-07-18Executing short pointer mode applications loaded in a memory address space having one portion addressable by short pointers and a shadow copy of the one portion
#38 | 2019-07-11Executing instructions to store context information based on routine to be executed
#39 | 2019-06-27Selective suppression of instruction translation lookaside buffer (ITLB) access
#40 | 2019-06-27Selective suppression of instruction cache-related directory access
#41 | 2019-06-20Debugging of prefixed code
#42 | 2019-05-30EMPLOYING A STACK ACCELERATOR FOR STACK-TYPE ACCESSES
#43 | 2019-05-16Address translation prior to receiving a storage reference using the address to be translated
#44 | 2019-05-16Memory based configuration state registers
#45 | 2019-05-16Protecting in-memory configuration state registers
#46 | 2019-05-16Context switch by changing memory pointers
#47 | 2019-05-16Single call to perform pin and unpin operations
#48 | 2019-05-16Bulk store and load operations of configuration state registers
#49 | 2019-05-16Configurable architectural placement control
#50 | 2019-05-16Portions of configuration state registers in-memory
#51 | 2019-05-16Separation of memory-based configuration state registers based on groups
#52 | 2019-05-16Configuration state registers grouped based on functional affinity
#53 | 2019-05-16Automatic pinning of units of memory
#54 | 2019-05-09Affinity domain-based garbage collection
#55 | 2019-05-09Locality domain-based memory pools for virtualized computing environment
#56 | 2019-05-09Facilitating access to memory locality domain information
#57 | 2019-04-18Selecting processing based on expected value of selected character
#58 | 2019-04-11Providing instructions to facilitate detection of corrupt stacks
#59 | 2019-04-11Selecting processing based on expected value of selected character
#60 | 2019-03-21Initializing a data structure for use in predicting table of contents pointer values
#61 | 2019-03-21Initializing a data structure for use in predicting table of contents pointer values
#62 | 2019-03-21Table of contents cache entry having a pointer for a range of addresses
#63 | 2019-03-21Set table of contents (TOC) register instruction
#64 | 2019-03-21Table of contents cache entry having a pointer for a range of addresses
#65 | 2019-03-21Set table of contents (TOC) register instruction
#66 | 2019-03-21Replacing table of contents (TOC)-setting instructions in code with TOC predicting instructions
#67 | 2019-03-21Replacing Table of Contents (TOC)-setting instructions in code with TOC predicting instructions
#68 | 2019-03-21Predicting a table of contents pointer value responsive to branching to a subroutine
#69 | 2019-03-21Predicting a table of contents pointer value responsive to branching to a subroutine
#70 | 2019-03-21Code generation relating to providing table of contents pointer values
#71 | 2019-03-21Code generation relating to providing table of contents pointer values
#72 | 2019-03-21Read-only table of contents register
#73 | 2019-03-21Read-only table of contents register
#74 | 2019-03-14Controlling a rate of prefetching based on bus bandwidth
#75 | 2019-03-14Controlling a rate of prefetching based on bus bandwidth
#76 | 2019-02-21Prediction of an affiliated register
#77 | 2019-02-21Predicting and storing a predicted target address in a plurality of selected locations
#78 | 2019-02-21Determining and predicting affiliated registers based on dynamic runtime control flow analysis
#79 | 2019-02-21Dynamic fusion of derived value creation and prediction of derived values in a subroutine branch sequence
#80 | 2019-02-21Determining and predicting derived values used in register-indirect branching
#81 | 2019-02-21Prediction of an affiliated register
#82 | 2019-02-21Determining and predicting derived values used in register-indirect branching
#83 | 2019-02-21Determining and predicting affiliated registers based on dynamic runtime control flow analysis
#84 | 2019-02-21Predicting and storing a predicted target address in a plurality of selected locations
#85 | 2019-02-21Dynamic fusion of derived value creation and prediction of derived values in a subroutine branch sequence
#86 | 2019-02-21Code-specific affiliated register prediction
#87 | 2019-02-21Concurrent prediction of branch addresses and update of register contents
#88 | 2019-02-21Providing a predicted target address to multiple locations based on detecting an affiliated relationship
#89 | 2019-02-21Concurrent prediction of branch addresses and update of register contents
#90 | 2019-02-21Providing a predicted target address to multiple locations based on detecting an affiliated relationship
#91 | 2019-02-14Context information based on type of routine being called
#92 | 2019-01-17Configurable code fingerprint
#93 | 2018-12-27Compiler controls for program regions
#94 | 2018-12-27Compiler controls for program regions
#95 | 2018-12-27Employing prefixes to control floating point operations
#96 | 2018-12-27Fine-grained management of exception enablement of floating point controls
#97 | 2018-12-27Predicted null updates
#98 | 2018-12-27Employing prefixes to control floating point operations
#99 | 2018-12-27Fine-grained management of exception enablement of floating point controls
#100 | 2018-12-27Predicted null updated
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