Fishkill, New York
United States
40
2014-06-26
The entities that hold a legal rights for patent applications filed by inventor Chanda Kaushik:
Kaushik Chanda from Fishkill, US has applied for patents for these inventions. The list has both pending applications and granted patents:
System involving electrically reprogrammable fuses
#2 | 2013-07-11Methods and systems involving electrically reprogrammable fuses
#3 | 2012-12-27E-fuse structures and methods of manufacture
#4 | 2012-10-04Stacked via structure for metal fuse applications
#5 | 2012-09-13Metal cap for back end of line (BEOL) interconnects, design structure and method of manufacture
#6 | 2012-07-05Method of manufacturing an interconnect structure and design structure thereof
#7 | 2012-05-10Method for fabricating air gap interconnect structures
#8 | 2012-05-03Interconnect structure with enhanced reliability
#9 | 2011-08-04Electrically programmable fuse and fabrication method
#10 | 2010-05-13Methods and systems involving electrically reprogrammable fuses
#11 | 2010-02-18Reliability of wide interconnects
#12 | 2010-02-18Interconnect structures, design structure and method of manufacture
#13 | 2010-02-18Electrically programmable fuse and fabrication method
#14 | 2009-12-03Stress locking layer for reliable metallization
#15 | 2009-12-03Interconnect structure for integrated circuits having improved electromigration characteristics
#16 | 2009-12-03Structure and method of forming electrically blown metal fuses for integrated circuits
#17 | 2009-06-25Methodology for Thermal Modeling of On-Chip Interconnects Based on Electromagnetic Simulation Tools
#18 | 2009-06-11Test structure for determining optimal seed and liner layer thicknesses for dual damascene processing
#19 | 2009-04-30Test structure for electromigration analysis and related method
#20 | 2009-03-19INTERCONNECT STRUCTURE WITH IMPROVED ELECTROMIGRATION RESISTANCE AND METHOD OF FABRICATING SAME
#21 | 2009-02-19METHODS AND SYSTEMS INVOLVING ELECTRICALLY REPROGRAMMABLE FUSES
#22 | 2009-02-05Test structure for electromigration analysis and related method
#23 | 2009-01-01Non-Destructive Electrical Characterization Macro and Methodology for In-Line Interconnect Spacing Monitoring
#24 | 2008-12-18Semiconductor wiring structures including dielectric cap within metal cap layer
#25 | 2008-09-25Structure for modeling stress-induced degradation of conductive interconnects
#26 | 2008-08-21Interconnect structure with bi-layer metal cap
#27 | 2008-07-24Method for prediction of premature dielectric breakdown in a semiconductor
#28 | 2008-07-03Addressable hierarchical metal wire test methodology
#29 | 2008-05-08Structure for monitoring stress-induced degradation of conductive interconnects
#30 | 2008-02-07Metal resistor and resistor material
#31 | 2007-12-20Metal resistor, resistor material and method
#32 | 2007-11-22Post chemical mechanical polishing etch for improved time dependent dielectric breakdown reliability
#33 | 2007-11-08INTERCONNECT METALLIZATION PROCESS WITH 100% OR GREATER STEP COVERAGE
#34 | 2007-07-12Method to improve time dependent dielectric breakdown
#35 | 2007-05-24Structure and method for monitoring stress-induced degradation of conductive interconnects
#36 | 2007-03-22Method of forming an interconnect including a dielectric cap having a tensile stress
#37 | 2007-02-15VIA bottom contact and method of manufacturing same
#38 | 2006-12-14METHOD FOR PREDICTION OF PREMATURE DIELECTRIC BREAKDOWN IN A SEMICONDUCTOR
#39 | 2006-11-16Method of forming interconnect structure or interconnect and via structures using post chemical mechanical polishing
#40 | 2006-05-11NANOSCALE DEFECT IMAGE DETECTION FOR SEMICONDUCTORS
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