Sailesh Kumar

Application mapping on hardened network-on-chip (NoC) of field-programmable gate array (FPGA)

System on chip (SoC) builder

Application mapping on hardened network-on-chip (NoC) of field-programmable gate array (FPGA)

BACKBONE NETWORK-ON-CHIP (NOC) FOR FIELD-PROGRAMMABLE GATE ARRAY (FPGA)

Automatic crossbar generation and router connections for network-on-chip (NOC) topology generation

SYSTEMS AND METHODS FOR MAINTAINING NETWORK-ON-CHIP (NOC) SAFETY AND RELIABILITY

Repository of integration description of hardware intellectual property for NoC construction and SoC integration

Buffer sizing of a NoC through machine learning

Generation of network-on-chip layout based on user specified topological constraints

Systems and methods for NoC construction

System-on-chip (SoC) optimization through transformation and generation of a network-on-chip (NoC) topology

Cost management against requirements for the generation of a NoC

Cost management against requirements for the generation of a NoC

Cost management against requirements for the generation of a NoC

Buffer sizing of a NoC through machine learning

Extracting features from a NoC for machine learning construction

Infrastructure to Apply Machine Learning for NoC Construction

Strategies for NoC Construction Using Machine Learning

Metrics to Train Machine Learning Predictor for NoC Construction

Interface virtualization and fast path for network on chip

TRAFFIC MAPPING OF A NETWORK ON CHIP THROUGH MACHINE LEARNING

TRAFFIC MAPPING OF A NETWORK ON CHIP THROUGH MACHINE LEARNING

TRAFFIC MAPPING OF A NETWORK ON CHIP THROUGH MACHINE LEARNING

Interface virtualization and fast path for Network on Chip

INTERFACE VIRTUALIZATION AND FAST PATH FOR NETWORK ON CHIP

SYSTEM AND METHOD FOR GROUPING OF NETWORK ON CHIP (NOC) ELEMENTS

Systems and methods for facilitating low power on a network-on-chip

Systems and methods for facilitating low power on a network-on-chip

Systems and methods for facilitating low power on a network-on-chip

Automatic generation of power management sequence in a SoC or NoC

AUTOMATIC GENERATION OF POWER MANAGEMENT SEQUENCE IN A SOC OR NOC

INTERFACE VIRTUALIZATION AND FAST PATH FOR NETWORK ON CHIP

Systems and methods for facilitating low power on a network-on-chip

QoS in a system with end-to-end flow control and QoS aware buffer allocation

Streaming bridge design with host interfaces and network on chip (NoC) layers

Generating physically aware network-on-chip design from a physical system-on-chip specification

Verification low power collateral generation

Automatic buffer sizing for optimal network-on-chip design

Automatic buffer sizing for optimal network-on-chip design

CONGESTION CONTROL AND QoS IN NoC BY REGULATING THE INJECTION TRAFFIC

Clock gating for system-on-chip elements

Hardware and software enabled implementation of power profile management instructions in system on chip

Automatic buffer sizing for optimal network-on-chip design

QoS in a system with end-to-end flow control and QoS aware buffer allocation

Heterogeneous channel capacities in an interconnect

Generation of network-on-chip layout based on user specified topological constraints

Heterogeneous SoC IP core placement in an interconnect to optimize latency and interconnect performance

SYSTEM AND METHOD FOR GROUPING OF NETWORK ON CHIP (NOC) ELEMENTS

Configurable router for a network on chip (NoC)

Clock gating for system-on-chip elements

Hierarchical asymmetric mesh with virtual routers

Dynamically configuring store-and-forward channels and cut-through channels in a network-on-chip

Supporting multicast in NoC interconnect

Automatic pipelining of NoC channels to meet timing and/or performance

System level simulation in Network on Chip architecture

Automatic performance characterization of a network-on-chip (NOC) interconnect

Automatic generation of physically aware aggregation/distribution networks

Transaction expansion for NoC simulation and NoC design

Hardware and software enabled implementation of power profile management instructions in system on chip

Automatic generation of power management sequence in a SoC or NoC

Automatic pipelining of NoC channels to meet timing and/or performance

Automatic power domain and voltage domain assignment to system-on-chip agents and network-on-chip elements

Specification for automatic power management of network-on-chip and system-on-chip

System and method for visualization of NoC performance based on simulation output

Integrated NoC for performing data communication and NoC functions

Using cuckoo movement for improved cache coherency

Transactional traffic specification for network-on-chip design

System and method for improving snoop performance

Systems and methods for selecting a router to connect a bridge in the network on chip (NoC)

Integrated NoC for performing data communication and NoC functions

QoS in a system with end-to-end flow control and QoS aware buffer allocation

Streaming bridge design with host interfaces and network on chip (NoC) layers

CACHE COHERENT NOC WITH FLEXIBLE NUMBER OF CORES, I/O DEVICES, DIRECTORY STRUCTURE AND COHERENCY POINTS

Automatic pipelining of NoC channels to meet timing and/or performance

Reuse of directory entries for holding state information through use of multiple formats

Using multiple traffic profiles to design a network on chip

NOC INTERFACE PROTOCOL ADAPTIVE TO VARIED HOST INTERFACE PROTOCOLS

Combining associativity and cuckoo hashing

Supporting multicast in NOC interconnect

Automatic NoC topology generation

System level simulation in network on chip architecture

Identification of internal dependencies within system components for evaluating potential protocol level deadlocks

Multiple clock domains in NoC

ASYMMETRIC MESH NOC TOPOLOGIES

Heterogeneous SoC IP core placement in an interconnect to optimize latency and interconnect performance

Congestion control and QoS in NoC by regulating the injection traffic

Multiple heterogeneous NoC layers

Reconfigurable NoC for customizing traffic and optimizing performance after NoC synthesis

Creating multiple NoC layers for isolation or avoiding NoC traffic congestion

QoS in heterogeneous NoC by assigning weights to NoC node channels and using weighted arbitration at NoC nodes

Automatic deadlock detection and avoidance in a system interconnect by capturing internal dependencies of IP cores using high level specification

Tagging and synchronization for fairness in NOC interconnects

Hierarchical asymmetric mesh with virtual routers

Asymmetric mesh NoC topologies

Asymmetric mesh NoC topologies

Heterogeneous channel capacities in an interconnect

Automatic construction of deadlock free interconnects

Asymmetric mesh NoC topologies

Memory mapping and translation for arbitrary number of memory units

High Performance Free Buffer Allocation and Deallocation