Coppell, Texas
United States
35
2011-02-03
The entities that hold a legal rights for patent applications filed by inventor Khamankar Rajesh:
Rajesh Khamankar from Coppell, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Laminated stress overlayer using In-situ multiple plasma treatments for transistor improvement
#2 | 2010-05-13Nitrogen based implants for defect reduction in strained silicon
#3 | 2009-09-10Gate structure and method
#4 | 2009-09-10Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps
#5 | 2009-06-18Laminated Stress Overlayer Using In-SITU Multiple Plasma Treatments for Transistor Improvement
#6 | 2009-05-19Gate structure and method
#7 | 2009-02-19Methodology for Reducing Post Burn-In Vmin Drift
#8 | 2008-10-16PMD liner nitride films and fabrication methods for improved NMOS performance
#9 | 2008-05-22Gate Dielectric Having a Flat Nitrogen Profile and Method of Manufacture Therefor
#10 | 2008-03-27REWORK METHODOLOGY THAT PRESERVES GATE PERFORMANCE
#11 | 2007-09-13Semiconductor device fabricated using a carbon-containing film as a contact etch stop layer
#12 | 2007-09-06CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers
#13 | 2007-06-07High performance CMOS transistors using PMD liner stress
#14 | 2007-05-24Reliable high voltage gate dielectric layers using a dual nitridation process
#15 | 2007-05-10Nitrogen based implants for defect reduction in strained silicon
#16 | 2007-02-27Reliable high voltage gate dielectric layers using a dual nitridation process
#17 | 2006-08-17Dual-gate integrated circuit semiconductor device
#18 | 2006-08-03Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps
#19 | 2006-07-13CMOS transistors and methods of forming same
#20 | 2006-05-23Post high voltage gate dielectric pattern plasma surface treatment
#21 | 2006-04-20Post high voltage gate oxide pattern high-vacuum outgas surface treatment
#22 | 2006-03-30Integration scheme to improve NMOS with poly cap while mitigating PMOS degradation
#23 | 2006-03-28Post high voltage gate oxide pattern high-vacuum outgas surface treatment
#24 | 2006-03-02Thermal treatment of nitrided oxide to improve negative bias thermal instability
#25 | 2006-03-02CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers
#26 | 2006-01-26Transistor fabrication methods using dual sidewall spacers
#27 | 2006-01-26Transistor fabrication methods using reduced width sidewall spacers
#28 | 2005-12-29Gate dielectric having a flat nitrogen profile and method of manufacture therefor
#29 | 2005-11-03High performance CMOS transistors using PMD liner stress
#30 | 2005-10-20PMD liner nitride films and fabrication methods for improved NMOS performance
#31 | 2005-07-28Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance
#32 | 2005-07-21Method for improving a physical property defect value of a gate dielectric
#33 | 2005-03-22Method for improving a physical property defect value of a gate dielectric
#34 | 2005-03-17CMOS transistors and methods of forming same
#35 | 2005-03-17Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance
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