Aloha, Oregon
United States
84
2025-10-16
The entities that hold a legal rights for patent applications filed by inventor Bohr Mark T.:
Mark T. Bohr from Aloha, US has applied for patents for these inventions. The list has both pending applications and granted patents:
THROUGH GATE FIN ISOLATION
#2 | 2025-09-25HYPERCHIP
#3 | 2025-07-24SELF-ALIGNED CONTACTS
#4 | 2025-07-10THROUGH GATE FIN ISOLATION
#5 | 2025-07-10MULTI VERSION LIBRARY CELL HANDLING AND INTEGRATED CIRCUIT STRUCTURES FABRICATED THEREFROM
#6 | 2025-02-27UNIFORM LAYOUTS FOR SRAM AND REGISTER FILE BIT CELLS
#7 | 2025-02-06GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING SOURCE OR DRAIN STRUCTURES WITH EPITAXIAL NUBS
#8 | 2024-10-31MULTI VERSION LIBRARY CELL HANDLING AND INTEGRATED CIRCUIT STRUCTURES FABRICATED THEREFROM
#9 | 2024-07-18HYPERCHIP
#10 | 2024-02-01Hyperchip
#11 | 2024-01-25Self-aligned contacts
#12 | 2023-10-12Uniform layouts for SRAM and register file bit cells
#13 | 2023-09-28REPLACEMENT METAL GATES TO ENHANCE TRANSISTOR STRAIN
#14 | 2023-07-27Hyperchip
#15 | 2023-05-18Self-aligned contacts
#16 | 2023-02-23Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs
#17 | 2022-11-10Semiconductor device having tipless epitaxial source/drain regions
#18 | 2022-05-12Multi version library cell handling and integrated circuit structures fabricated therefrom
#19 | 2022-05-05Distributed semiconductor die and package architecture
#20 | 2022-01-27Integrated circuit device with crenellated metal trace layout
#21 | 2021-12-02FUNCTIONALLY REDUNDANT SEMICONDUCTOR DIES AND PACKAGE
#22 | 2021-07-29THROUGH GATE FIN ISOLATION
#23 | 2021-07-22Hyperchip
#24 | 2021-06-24Techniques for die stacking and associated configurations
#25 | 2021-05-06Self-aligned contacts
#26 | 2021-04-15Integrated circuit device with back-side interconnection to deep source/drain semiconductor
#27 | 2020-11-12Multi version library cell handling and integrated circuit structures fabricated therefrom
#28 | 2020-10-22Semiconductor device having tipless epitaxial source/drain regions
#29 | 2020-10-01Distributed semiconductor die and package architecture
#30 | 2020-09-24Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs
#31 | 2020-09-03Power shared cell architecture
#32 | 2020-08-06Self-aligned contacts
#33 | 2020-05-07ACTIVE SILICON BRIDGE
#34 | 2020-02-27Hyperchip
#35 | 2020-02-27Multiple reticle field semiconductor devices
#36 | 2020-02-20Semiconductor device having tipless epitaxial source/drain regions
#37 | 2020-02-20Uniform layouts for SRAM and register file bit cells
#38 | 2019-10-10Integrated circuit device with crenellated metal trace layout
#39 | 2019-08-29Metal on both sides with power distributed through the silicon
#40 | 2019-08-22Integrated circuit device with back-side interconnection to deep source/drain semiconductor
#41 | 2019-07-18Distributed semiconductor die and package architecture
#42 | 2019-07-04Functionally redundant semiconductor dies and package
#43 | 2019-04-25Via blocking layer
#44 | 2019-02-14Self-aligned contacts
#45 | 2018-08-02Metal on both sides with power distributed through the silicon
#46 | 2018-06-21Via blocking layer
#47 | 2018-04-05Self-aligned contacts
#48 | 2017-11-23Semiconductor device having tipless epitaxial source/drain regions
#49 | 2017-11-16Via blocking layer
#50 | 2017-02-09Self-aligned contacts
#51 | 2016-08-25Replacement metal gates to enhance transistor strain
#52 | 2016-06-02Self-aligned contacts
#53 | 2016-05-12Semiconductor device having tipless epitaxial source/drain regions
#54 | 2016-02-18Replacement metal gates to enhance tranistor strain
#55 | 2015-12-173D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach
#56 | 2015-11-193D integrated circuit package with window interposer
#57 | 2015-09-24Self-aligned contacts
#58 | 2015-07-02DIE PACKAGE ARCHITECTURE WITH EMBEDDED DIE AND SIMPLIFIED REDISTRIBUTION LAYER
#59 | 2015-04-16Replacement metal gates to enhance transistor strain
#60 | 2014-07-103D integrated circuit package with window interposer
#61 | 2014-06-05Self-aligned contacts
#62 | 2014-01-02Through gate fin isolation
#63 | 2013-10-313D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach
#64 | 2013-10-10Replacement gates to enhance transistor strain
#65 | 2013-10-033D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias
#66 | 2013-09-19Semiconductor device having tipless epitaxial source/drain regions
#67 | 2013-08-29Penetrating implant for forming a semiconductor device
#68 | 2013-07-11Self-aligned contacts
#69 | 2012-01-05REPLACEMENT GATES TO ENHANCE TRANSISTOR STRAIN
#70 | 2011-09-08Penetrating implant for forming a semiconductor device
#71 | 2011-06-30Self-aligned contacts
#72 | 2009-10-01Penetrating implant for forming a semiconductor device
#73 | 2009-03-05Replacement gates to enhance transistor strain
#74 | 2008-11-20Semiconductor device having tipless epitaxial source/drain regions
#75 | 2008-06-12Transistor with improved tip profile and method of manufacture thereof
#76 | 2007-06-21Silicide layers in contacts for high-k/metal gate transistors
#77 | 2007-06-21Replacement gates to enhance transistor strain
#78 | 2007-01-04Transistor with improved tip profile and method of manufacture thereof
#79 | 2005-10-20Method and apparatus for improved power routing
#80 | 2005-07-21Hermetic passivation structure with low capacitance
#81 | 2005-06-23Method and apparatus for improved power routing
#82 | 2005-05-03On-die de-coupling capacitor using bumps or bars
#83 | 2005-04-05Wafer passivation structure and method of fabrication
#84 | 2005-01-27Interposer and method of making same
335154 ⎘