Austin, Texas
United States
33
2022-05-19
The entities that hold a legal rights for patent applications filed by inventor McDonald Thomas C.:
Thomas C. McDonald from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Spectre fixes with predictor mode tag
#2 | 2022-05-19Side cache array for greater fetch bandwidth
#3 | 2022-05-19Spectre fixes with indirect valid table
#4 | 2022-05-12Small branch predictor escape
#5 | 2022-05-05Branch density detection for prefetcher
#6 | 2022-04-28Dual branch format
#7 | 2022-04-28Dual branch execute and table update with single port
#8 | 2022-04-21Quick predictor override and update by a BTAC
#9 | 2022-03-15Adjustable write policies controlled by feature control registers
#10 | 2011-03-03Efficient branch target address cache entry replacement
#11 | 2011-01-20Out-of-order microprocessor with separate branch information circular queue table tagged by branch instructions in reorder buffer to reduce unnecessary space in buffer
#12 | 2010-11-25Apparatus and method for marking start and end bytes of instructions in a stream of instruction bytes in a microprocessor having an instruction set architecture in which instructions may include a length-modifying prefix
#13 | 2010-11-25Bad branch prediction detection, marking, and accumulation for faster instruction stream processing
#14 | 2010-11-25Instruction extraction through prefix accumulation
#15 | 2010-11-25Prefix accumulation for efficient processing of instructions with multiple prefix bytes
#16 | 2010-11-25Apparatus for efficiently determining instruction length instruction within a stream of x86 instruction bytes
#17 | 2010-11-25Early release of cache data with start/end marks when instructions are only partially present
#18 | 2007-04-12Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence
#19 | 2007-04-03Apparatus and method for speculatively performing a return instruction in a microprocessor
#20 | 2007-02-13Method and apparatus for correcting an internal call/return stack in a microprocessor that detects from multiple pipeline stages incorrect speculative update of the call/return stack
#21 | 2007-01-16Speculative branch target address cache with selective override by secondary predictor based on branch instruction type
#22 | 2006-11-07Microprocessor that detects erroneous speculative prediction of branch instruction opcode byte
#23 | 2006-01-12Apparatus and method for handling BTAC branches that wrap across instruction cache lines
#24 | 2005-12-01Variable group associativity branch target address cache delivering multiple target addresses per cache line
#25 | 2005-09-22Processor including fallback branch prediction mechanism for far jump and far call instructions
#26 | 2005-09-08Apparatus and method for densely packing a branch instruction predicted by a branch target address cache and associated target instructions into a byte-wide instruction buffer
#27 | 2005-09-08Apparatus and method for handling BTAC branches that wrap across instruction cache lines
#28 | 2005-06-30Processor including branch prediction mechanism for far jump and far call instructions
#29 | 2005-06-16Speculative hybrid branch direction predictor
#30 | 2005-05-26Apparatus and method for target address replacement in speculative branch target address cache
#31 | 2005-05-17Apparatus and method for target address replacement in speculative branch target address cache
#32 | 2005-04-26Speculative hybrid branch direction predictor
#33 | 2005-02-24Selecting next instruction line buffer stage based on current instruction line boundary wraparound and branch target in buffer indicator
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