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Inventor profile of:

PETER LACHNER

City:

Heroldstatt

Country:

Germany

Published Applications:

25

Last publication date:

2021-03-25

Top Assignees for applications by PETER LACHNER

The entities that hold a legal rights for patent applications filed by inventor LACHNER PETER:

INTEL CORPORATION 19 Santa Clara, CA United States
Intel IP Corporation 1 Santa Clara, CA United States
MICROSOFT CORPORATION 1 Redmond, WA United States

Recent patent applications by LACHNER PETER

PETER LACHNER from Heroldstatt, DE has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2021-03-25

US20210089427A1

System, apparatus and method for dynamic tracing in a system

#2 | 2020-09-10

US20200285559A1

SYSTEM, APPARATUS AND METHOD FOR DYNAMIC TRACING IN A SYSTEM HAVING ONE OR MORE VIRTUALIZATION ENVIRONMENTS

#3 | 2019-12-05

US20190370503A1

Functional safety over trace-and-debug

#4 | 2019-06-27

US20190196931A1

System, apparatus and method for dynamic multi-source tracing in a system

#5 | 2019-02-14

US20190050021A1

Multichip reference logging synchronization

#6 | 2018-05-31

US20180150301A9

GATHERING AND SCATTERING MULTIPLE DATA ELEMENTS

#7 | 2018-05-10

US20180129506A1

Gathering and scattering multiple data elements

#8 | 2016-12-29

US20160378636A1

Software-Initiated Trace Integrated with Hardware Trace

#9 | 2016-08-11

US20160232041A1

Last branch record indicators for transactional memory

#10 | 2016-06-16

US20160170820A1

Tracking deferred data packets in a debug trace architecture

#11 | 2015-01-01

US20150006717A1

Tracking mode of a processing device in instruction tracing systems

#12 | 2014-12-18

US20140372987A1

Processor that records tracing data in non contiguous system memory slices

#13 | 2014-11-20

US20140344553A1

Gathering and scattering multiple data elements

#14 | 2014-11-20

US20140344552A1

Providing status of a processing device with periodic synchronization point in instruction tracing system

#15 | 2014-09-11

US20140258695A1

Last branch record register for storing taken branch information and transactional memory transaction indicator to be used in transaction execution analysis

#16 | 2013-10-03

US20130263093A1

Optional logging of debug activities in a real time instruction tracing log

#17 | 2013-07-11

US20130179668A1

Last branch record indicators for transactional memory

#18 | 2012-02-02

US20120030518A1

Processor with last branch record register storing transaction indicator

#19 | 2011-08-11

US20110197182A1

Debugging parallel software using speculatively executed code sequences in a multiple core environment

#20 | 2011-06-23

US20110154303A1

Endian conversion tool

#21 | 2011-06-23

US20110153983A1

Gathering and scattering multiple data elements

#22 | 2011-06-16

US20110145798A1

Debugging mechanisms in a cache-based memory isolation system

#23 | 2010-06-17

US20100153934A1

Prefetch for systems with heterogeneous architectures

#24 | 2009-12-31

US20090327937A1

Methods and apparatus for analyzing SIMD code

#25 | 2006-08-29

US10278400

Controlling the timing of test modes in a multiple processor system

InventorID:

338150 ⎘