Inventor profile of:

Krishnakanth V. Sistla

City:

Beaverton, Oregon

Country:

United States

Published Applications:

76

Last publication date:

2023-08-10

Top Assignees for applications by Krishnakanth V. Sistla

The entities that hold a legal rights for patent applications filed by inventor Sistla Krishnakanth V.:

Recent patent applications by Sistla Krishnakanth V.

Krishnakanth V. Sistla from Beaverton, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2023-08-10
US20230251702A1
Physics

OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS TO PMU

#2 | 2021-03-04
US20210064117A1
Physics

OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS TO PMU

#3 | 2021-03-04
US20210064110A1
Physics

CONTROL BLOCKS FOR PROCESSOR POWER MANAGEMENT

#4 | 2020-10-22
US20200334193A1
Physics

Dynamically updating logical identifiers of cores of a processor

#5 | 2020-10-22
US20200333867A1
Physics

Current control for a multicore processor

#6 | 2020-10-08
US20200319693A1
Physics

Hybrid prioritized resource allocation in thermally-or power-constrained computing devices

#7 | 2020-09-24
US20200301490A1
Physics

Apparatus and method to provide a thermal parameter report for a multi-chip package

#8 | 2020-08-27
US20200272513A1
Physics

Thread Scheduling Using Processing Engine Information

#9 | 2019-12-19
US20190384348A1
Physics

Configuration of base clock frequency of processor based on usage parameters

#10 | 2019-10-17
US20190317773A1
Physics

Collaborative processor and system performance and power management

#11 | 2019-04-04
US20190102221A1
Physics

Thread scheduling using processing engine information

#12 | 2019-04-04
US20190101969A1
Physics

Control Blocks for Processor Power Management

#13 | 2019-02-07
US20190042348A1
Physics

Techniques to collect crash data for a computing system

#14 | 2019-02-07
US20190041949A1
Physics

Hybrid prioritized resource allocation in thermally- or power-constrained computing devices

#15 | 2018-12-20
US20180365022A1
Physics

DYNAMIC OFFLINING AND ONLINING OF PROCESSOR CORES

#16 | 2018-12-13
US20180356868A1
Physics

Adaptive parameterization for maximum current protection

#17 | 2018-11-22
US20180336111A1
Physics

System, Apparatus And Method For Performing In-Field Self-Testing Of A Processor

#18 | 2018-07-12
US20180196488A1
Physics

Method and apparatus to control a link power state

#19 | 2018-06-21
US20180173298A1
Physics

AVERAGE CURRENT PROTECTION MECHANISM

#20 | 2018-04-12
US20180101502A1
Physics

Multiple dies hardware processors and methods

#21 | 2018-03-08
US20180067892A1
Physics

Dynamically updating logical identifiers of cores of a processor

#22 | 2017-12-21
US20170364132A1
Physics

Current control for a multicore processor

#23 | 2017-11-23
US20170337131A1
Physics

Resolving multi-core shared cache access conflicts

#24 | 2017-11-16
US20170329377A1
Physics

Supercapacitor-based power supply protection for multi-node systems

#25 | 2017-10-05
US20170285710A1
Physics

Processor power monitoring and control with dynamic load balancing

#26 | 2017-06-22
US20170177046A1
Physics

Controlling telemetry data communication in a processor

#27 | 2017-05-25
US20170149554A1
Electricity

Changing the clock frequency of a computing device

#28 | 2017-04-27
US20170115716A1
Physics

Mechanism to provide workload and configuration-aware deterministic performance for microprocessors

#29 | 2017-04-13
US20170102752A1
Physics

Forcing core low power states in a processor

#30 | 2017-03-23
US20170083076A1
Physics

User level control of power management policies

#31 | 2017-02-02
US20170031412A1
Physics

Masking a power state of a core of a processor

#32 | 2017-01-19
US20170017292A1
Physics

OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS TO PMU

#33 | 2017-01-19
US20170017286A1
Physics

Optimizing power usage by factoring processor architectural events to PMU

#34 | 2017-01-05
US20170003724A1
Physics

Collaborative processor and system performance and power management

#35 | 2016-12-29
US20160378486A1
Physics

Method and apparatus for execution mode selection

#36 | 2016-12-29
US20160378173A1
Physics

Tracking missed periodic actions across state domains

#37 | 2016-09-15
US20160266941A1
Physics

Dynamically modifying a power/performance tradeoff based on a processor utilization

#38 | 2016-09-01
US20160252943A1
Physics

Dynamically updating logical identifiers of cores of a processor

#39 | 2016-09-01
US20160252942A1
Physics

Supercapacitor-based power supply protection for multi-node systems

#40 | 2016-08-18
US20160239068A1
Physics

Performing dynamic power control of platform devices

#41 | 2016-07-07
US20160195913A1
Physics

OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS TO PMU

#42 | 2016-06-30
US20160187952A1
Physics

Method and apparatus to control a link power state

#43 | 2016-06-23
US20160179158A1
Physics

Apparatus and method to provide a thermal parameter report for a multi-chip package

#44 | 2016-01-21
US20160018883A1
Physics

Dynamic power limit sharing in a platform

#45 | 2016-01-07
US20160004291A1
Physics

User level control of power management policies

#46 | 2015-12-31
US20150377955A1
Physics

Apparatus and method for a user configurable reliability control loop

#47 | 2015-10-08
US20150286266A1
Physics

Controlling configurable peak performance limits of a processor

#48 | 2015-09-24
US20150269105A1
Physics

Utilization-aware low-overhead link-width modulation for power reduction in interconnects

#49 | 2015-09-10
US20150254118A1
Physics

Virtualized communication sockets for multi-flow access to message channel infrastructure within CPU

#50 | 2015-08-27
US20150241949A1
Physics

Mechanism to provide workload and configuration-aware deterministic performance for microprocessors

#51 | 2015-07-02
US20150186278A1
Physics

RUNTIME PERSISTENCE

#52 | 2015-05-07
US20150127962A1
Physics

Optimizing power usage by factoring processor architectural events to PMU

#53 | 2015-03-26
US20150089287A1
Physics

EVENT-TRIGGERED STORAGE OF DATA TO NON-VOLATILE MEMORY

#54 | 2015-03-05
US20150067361A1
Physics

Adaptively controlling low power mode operation for a cache memory

#55 | 2015-02-26
US20150058650A1
Physics

Forcing core low power states in a processor

#56 | 2015-01-01
US20150006971A1
Physics

Apparatus and method for controlling the reliability stress rate on a processor

#57 | 2014-09-18
US20140281612A1
Physics

Measurement of performance scalability in a microprocessor

#58 | 2014-09-18
US20140281445A1
Physics

Processor having frequency of operation information for guaranteed operation under high temperature events

#59 | 2014-07-10
US20140195828A1
Physics

Dynamically measuring power consumption in a processor

#60 | 2014-07-03
US20140189694A1
Physics

Managing performance policies based on workload scalability

#61 | 2014-06-26
US20140181596A1
Physics

Wear-out equalization techniques for multiple functional units

#62 | 2014-06-26
US20140181538A1
Physics

Controlling configurable peak performance limits of a processor

#63 | 2014-06-26
US20140176581A1
Physics

Controlling configurable peak performance limits of a processor

#64 | 2014-06-19
US20140173297A1
Physics

Performing frequency coordination in a multiprocessor system

#65 | 2014-06-19
US20140173248A1
Physics

Performing frequency coordination in a multiprocessor system based on response timing optimization

#66 | 2014-05-08
US20140129858A1
Physics

Method and apparatus for setting an I/O bandwidth-based processor frequency floor

#67 | 2014-01-02
US20140006761A1
Physics

Mechanism to provide workload and configuration-aware deterministic performance for microprocessors

#68 | 2014-01-02
US20140006673A1
Physics

Utilization-aware low-overhead link-width modulation for power reduction in interconnects

#69 | 2013-12-12
US20130332753A1
Physics

Dynamic power limit sharing in a platform

#70 | 2013-10-17
US20130275796A1
Physics

Collaborative processor and system performance and power management

#71 | 2013-10-17
US20130275737A1
Physics

Collaborative processor and system performance and power management

#72 | 2013-07-11
US20130179706A1
Physics

User level control of power management policies

#73 | 2013-06-13
US20130151569A1
Physics

Computing platform interface with memory management

#74 | 2012-08-09
US20120204042A1
Physics

User level control of power management policies

#75 | 2012-07-19
US20120185706A1
Physics

Method, apparatus, and system for energy efficiency and energy conservation including dynamic control of energy consumption in power domains

#76 | 2012-06-07
US20120144217A1
Physics

Dynamically modifying a power/performance tradeoff based on processor utilization

InventorID:

338205 ⎘