Phil P. Marcoux

City:

Mountain View, California

Country:

United States

Published Applications:

Last publication date:

2011-07-14

Top Assignees for applications by Phil P. Marcoux

The entities that hold a legal rights for patent applications filed by inventor Marcoux Phil P.:

WAFER-LEVEL PACKAGING PORTFOLIO LLC 4 Cupertino, CA United States
ChipScale, Inc. 2 San Jose, CA United States
INTERCONNECT PORTFOLIO LLC 1 Cupertino, CA United States
SAMSUNG ELECTRONICS CO., LTD. 1 Gyeonggi-Do, South Korea

Recent patent applications by Marcoux Phil P.

Phil P. Marcoux from Mountain View, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2011-07-14

US20110169171A1

Electricity

Dual Interconnection in Stacked Memory and Controller Module

#2 | 2011-04-07

US20110079912A1

Electricity

Connection for off-chip electrostatic discharge protection

#3 | 2010-12-30

US20100327448A1

Chemistry; metallurgy

Semiconductor with Bottom-Side Wrap-Around Flange Contact

#4 | 2010-10-28

US20100270668A1

Electricity

Dual Interconnection in Stacked Memory and Controller Module

#5 | 2009-12-31

US20090324906A1

Electricity

SEMICONDUCTOR WITH TOP-SIDE WRAP-AROUND FLANGE CONTACT

#6 | 2009-12-31

US20090321930A1

Chemistry; metallurgy

Semiconductor with bottom-side wrap-around flange contact

#7 | 2005-10-11

US10071581

Integrated passive components and package with posts

#8 | 2005-09-20

US10783676

Integrated passive components and package with posts

InventorID:

3420134 ⎘