Pleasanton, California
United States
28
2023-08-17
The entities that hold a legal rights for patent applications filed by inventor LEE Peter:
Peter LEE from Pleasanton, US has applied for patents for these inventions. The list has both pending applications and granted patents:
INTERFACE LEVEL-SHIFTER DUAL-RAIL MEMORY ARCHITECTURE
#2 | 2019-08-22Fabricating memory devices with optimized gate oxide thickness
#3 | 2018-07-31Dual-port memories and input/output circuits for preventing failures corresponding to concurrent accesses of dual-port memory cells
#4 | 2018-05-03Fabricating memory devices with optimized gate oxide thickness
#5 | 2017-12-07Integrated circuit manufacturing process for aligning threshold voltages of transistors
#6 | 2017-11-28Systems and methods for a high performance memory cell structure
#7 | 2017-01-31Disturb-proof static RAM cells
#8 | 2016-12-08SYSTEMS AND METHODS FOR INCREASING PACKING DENSITY IN A SEMICONDUCTOR CELL ARRAY
#9 | 2016-04-26Systems and methods for avoiding read disturbance in a static random-access memory (SRAM)
#10 | 2016-03-24Resistive random access memory cell structure
#11 | 2016-03-01Systems and methods for increasing the read sensitivity of a resistive random access memory (RRAM)
#12 | 2016-01-26Reducing source contact to gate spacing to decrease transistor pitch
#13 | 2015-09-29Resistive memory cell and method for forming a resistive memory cell
#14 | 2015-07-09Method and apparatus for screening memory cells for disturb failures
#15 | 2015-05-07Resistive random access memory cell structure with reduced programming voltage
#16 | 2015-03-05Method and apparatus for reforming a memory cell of a memory
#17 | 2015-02-03System and method for creating a bipolar resistive RAM (RRAM)
#18 | 2014-06-19Resistive random access memory and method for controlling manufacturing of corresponding sub-resolution features of conductive and resistive elements
#19 | 2014-05-15Concurrent use of SRAM cells with both NMOS and PMOS pass gates in a memory system
#20 | 2014-05-01SRAM cells suitable for Fin field-effect transistor (FinFET) process
#21 | 2014-04-24Apparatus and method for reforming resistive memory cells
#22 | 2014-04-17Method and apparatus for forming a contact in a cell of a resistive random access memory to reduce a voltage required to program the cell
#23 | 2014-04-17Configuring resistive random access memory (RRAM) array for write operations
#24 | 2014-04-17Systems and methods for reading resistive random access memory (RRAM) cells
#25 | 2014-04-17Apparatus and method for repairing resistive memories and increasing overall read sensitivity of sense amplifiers
#26 | 2013-11-07Circuits and methods for calibrating offset in an amplifier
#27 | 2013-07-18System and method for modifying activation of a sense amplifier
#28 | 2011-06-16Circuits and methods for calibrating offset in an amplifier
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