Synopsys, Inc.

On-chip supply transient drop and supply transient bump detection

Hardened memory device noise protection

Analog references for high voltage input-output with improved bias current

Block virtualization for multi-threaded electronic design automation read/write database access

Block virtualization for multi-threaded electronic design automation read/write database access

Error-correcting and error-detecting parity-check matrix to store a known bad data bit in a memory system

Low contention high reference offset tolerant level shifter

Input/output (IO) failsafe protection topology in leaky technology nodes

Memory data inversion

Asynchronous SAR ADC with detection and correction circuit for large amplitude output code errors

Adding scalar blinding in elliptic curve cryptography

Analog amplitude control circuit to optimize drive level of crystal oscillator

High-speed octal-rate wireline transmitters

Manufacturing automatic test equipment and field ambient comparison with silicon lifecycle management support

Josephson junction structures

License server caching for checkout of floating licenses

Automatic waiver generation for filtering violations reported by static analysis

Bitcell power tracking scheme for transient voltage collapse write assist

Logic built-in self-test (LBIST) circuit for authenticity validation

Caching outputs of components in signal-flow-based simulations

Dynamic ordering of design rule checks

Power routing reduction in circuit design for electrostatic discharge checking

Static random access memory cell

Constant transconductance-resistance tracking circuit for complementary metal oxide semiconductor amplifiers

Memristor-enabled programmable sensing and switching threshold adjustment

Voltage scalable fail-safe IO drivers

Modifying the topology of circuits containing mixed signal subcircuits to enable electro-optical co-simulation

Path margin monitoring

Thread data race detection and synchronization for parallel implementation of verification testbenches

Pattern-based hierarchy exploration for compressing an integrated circuit design layout

Low power area efficient adaptive load compensation

Identifying circuit elements and/or ports for threat analysis and risk assessment

Optimization of circuit design layout using dynamic probability of success of component placement in integrated circuit design

Signoff-safe multi-corner reduction for static timing analysis

Dynamic frequency supported time division multiplexing interface

Performance and throughput when modeling half cycle paths during emulation or prototyping

Preserving switching activity during integrated circuit optimization

Bleeder and reset for static random access memory

Pointer information encoded in weighted increment signals

Associating physical design metrics of a circuit design with register transfer level representations of the circuit design

Neighborhood built-in self-test noise generation

Integrated circuit test pattern interleaving

Digital calibration of non-linearity in a programmable clock phase circuit

Half static random access memory (SRAM) cell

Application-specific integrated circuit (ASIC) synthesis based on lookup table (LUT) mapping and optimization

Logic verification of superconducting electronic circuits, including for margin analysis of yield

Cloud enabled hardware simulation with smart reuse of historical data

Machine-learning model for circuit design requirements verification

Non-retention mode leakage reduction without impacting the cell content in the retention mode

Voltage scalable level shifter

Connectivity controller with enhanced throughput in an embedded system

Negative discharge circuit

Media access control (MAC) to physical coding sublayer (PCS) data rate synchronization circuitry

Creating scanning plans for improving accuracy and resolution of optical wafer inspection

Resonance mitigation for a system-on-chip memory subsystem

Dynamic NAND sensing for a memory read operation

Control of low-power checkers using assertion control techniques of assertions language

Recursive doubling decision feedback equalizer

Preemptive stoppage of design clocks for processing blocking direct programming interface calls

Configurable delay chain

Performing time-efficient clock engineering change orders (ECO)

Representing lithographic layouts using parametric curves

Dual-error correcting code (ECC) for metadata in memory system

Maximizing detectable defect coverage of analog circuits in integrated circuit design

Interposer routing for universal chiplet interconnect express™ channels by partitioning into subchannels

Simultaneous multi-scenario static noise analysis

Dynamically configurable system-on-chip network

Memory with hybrid write assist scheme

Supply voltage droop detector

INTELLIGENT REPLAY OF SIMULATION ON MODIFIED CONSTRAINT RANDOM TESTBENCH

Memory Cell Noise Protection via Bidirectional Threshold Switching Devices

Adiabatic quantum-flux-parametron placement

Gray code counter enabled to increment by greater than one

Determining a density of through-silicon vias in integrated circuits

Performing timing constraint equivalence checking on circuit designs

In-situ function parameter search space filtering for machine learning in electronic design automation

MEMORY CELL WITH DYNAMIC DISTURB REDUCTION

Performing automatic sign-off for clock gating verification using toggle cover properties

Multi-machine version independent hierarchical verification

Hardware security checks in static verification of integrated circuit designs

Solving multiple array problems interacting with each other in constraint solving for functional verification of logic designs

Stacked nanosheet device for process and performance optimization

Automatic design parameter optimization for electronic circuit designs with operating environment coverage

Placing hard macros using machine learning predictions trained on different circuit designs

Driver/inverter using lower voltage tolerant devices

Memory protection unit with secure delegation

Duty-cycle matched differential clock divider circuit

Combined global and local process variation modeling

Transmitter driver circuit

Fail tolerant pad sensor circuit

Modifying a current circuit design using data from one or more previous circuit designs identified as being similar to the current circuit design

Decision feedback equalizer with feedforward finite impulse response filter

Modifying scan patterns to enable broadcasting a scan enable signal to multiple circuit blocks

Superconducting anti-fuse based field programmable gate array

Dynamic power efficient low power flip-flop

Constrained random simulation using machine learning and Bayesian estimation

Predicting tests based on change-list descriptions