Synopsys, Inc.

Bleeder and reset for static random access memory

Pointer information encoded in weighted increment signals

Associating physical design metrics of a circuit design with register transfer level representations of the circuit design

Neighborhood built-in self-test noise generation

Integrated circuit test pattern interleaving

Digital calibration of non-linearity in a programmable clock phase circuit

Half static random access memory (SRAM) cell

Application-specific integrated circuit (ASIC) synthesis based on lookup table (LUT) mapping and optimization

Logic verification of superconducting electronic circuits, including for margin analysis of yield

Cloud enabled hardware simulation with smart reuse of historical data

Machine-learning model for circuit design requirements verification

Non-retention mode leakage reduction without impacting the cell content in the retention mode

Voltage scalable level shifter

Connectivity controller with enhanced throughput in an embedded system

Negative discharge circuit

Media access control (MAC) to physical coding sublayer (PCS) data rate synchronization circuitry

Creating scanning plans for improving accuracy and resolution of optical wafer inspection

Resonance mitigation for a system-on-chip memory subsystem

Dynamic NAND sensing for a memory read operation

Control of low-power checkers using assertion control techniques of assertions language

Recursive doubling decision feedback equalizer

Preemptive stoppage of design clocks for processing blocking direct programming interface calls

Configurable delay chain

Performing time-efficient clock engineering change orders (ECO)

Representing lithographic layouts using parametric curves

Dual-error correcting code (ECC) for metadata in memory system

Maximizing detectable defect coverage of analog circuits in integrated circuit design

Interposer routing for universal chiplet interconnect express™ channels by partitioning into subchannels

Simultaneous multi-scenario static noise analysis

Dynamically configurable system-on-chip network

Memory with hybrid write assist scheme

Supply voltage droop detector

INTELLIGENT REPLAY OF SIMULATION ON MODIFIED CONSTRAINT RANDOM TESTBENCH

Adiabatic quantum-flux-parametron placement

Gray code counter enabled to increment by greater than one

Determining a density of through-silicon vias in integrated circuits

Performing timing constraint equivalence checking on circuit designs

In-situ function parameter search space filtering for machine learning in electronic design automation

MEMORY CELL WITH DYNAMIC DISTURB REDUCTION

Performing automatic sign-off for clock gating verification using toggle cover properties

Multi-machine version independent hierarchical verification

Hardware security checks in static verification of integrated circuit designs

Solving multiple array problems interacting with each other in constraint solving for functional verification of logic designs

Stacked nanosheet device for process and performance optimization

Automatic design parameter optimization for electronic circuit designs with operating environment coverage

Placing hard macros using machine learning predictions trained on different circuit designs

Driver/inverter using lower voltage tolerant devices

Memory protection unit with secure delegation

Duty-cycle matched differential clock divider circuit

Combined global and local process variation modeling

Transmitter driver circuit

Fail tolerant pad sensor circuit

Modifying a current circuit design using data from one or more previous circuit designs identified as being similar to the current circuit design

Decision feedback equalizer with feedforward finite impulse response filter

Modifying scan patterns to enable broadcasting a scan enable signal to multiple circuit blocks

Superconducting anti-fuse based field programmable gate array

Dynamic power efficient low power flip-flop

Constrained random simulation using machine learning and Bayesian estimation

Predicting tests based on change-list descriptions

Virtual isolated pattern layer: isolated pattern recognition, extraction and compression

ALIGNMENT MARKER ACQUISITION CIRCUITRY FOR A COMMUNICATION SYSTEM

Interconnects, inductors, transformers, and power architectures for circuits

Constant-gain bias circuit

ONE-TIME PROGRAMMABLE BITCELL WITH A THERMALLY ENHANCED RUPTURE

Semiconductor process simulation on graphics processing unit (GPU) with multi-level data structure

Memory with external clock synchronized operation

Validating test patterns ported between different levels of a hierarchical design of an integrated circuit

Side-channel resilient public key cryptography

Configurable transmitter architecture for supporting multiple data rates

Machine-learning-based design-for-test (DFT) recommendation system for improving automatic test pattern generation (ATPG) quality of results (QoR)

EVENT-DRIVEN TRACING IN STATIC TIMING ANALYSIS OF DIGITAL CIRCUIT DESIGNS

Delay circuit

Pay-per-use metering service for electronic design automation workloads in the cloud

Failure prediction of field-deployed mission critical integrated circuit chips using artificial intelligence

Partitioning a circuit for distributed balanced independent simulation jobs with upper-bounded memory

MEMORY ADDRESS CACHING FOR NEURAL NETWORKS

Scan chain formation for improving chain resolution

Address mapping for a memory system

Finding equivalent classes of hard defects in stacked MOSFET arrays

Memory profiler for emulation

Dynamic clock scaling using compression and serialization

Glitch identification and power analysis using simulation vectors

IN SITU DELAY MEASUREMENTS ON INTEGRATED CIRCUITS USING LIVE DATA AND PULSE WIDTH MODULATION

Memory write assist

Output driver level-shifting latch circuit for dual-rail memory

Method and system for transmission power control in bluetooth low energy controllers

Superconductive integrated circuit devices with on-chip testing

Configurable, high speed and high voltage tolerant output driver

Power efficient retention flip flop circuit

Timing path analysis using flow graphs

Line driver with high over-voltage protection

DYNAMIC JOB DEPENDENCY DISCOVERY AND CONSTRAINTS GENERATION TO SCHEDULE EDA WORKLOADS IN CLOUD ENVIRONMENTS

ADAPTIVE HARDWARE TRACING

Early detection of single bit error on address and data

Incremental clock tree planning

Multi level loopback to enable automated testing of standalone connectivity controller