Qiang Chen

City:

Sollentuna

Country:

Sweden

Published Applications:

Last publication date:

2011-12-01

Top Assignees for applications by Qiang Chen

The entities that hold a legal rights for patent applications filed by inventor Chen Qiang:

Qiang Chen from Sollentuna, SE has applied for patents for these inventions. The list has both pending applications and granted patents:

Method and layout of semiconductor device with reduced parasitics

Method and layout of semiconductor device with reduced parasitics

Integrated circuit ESD protection

LDMOS transistor

InventorID:

3486826 ⎘