INFINEON TECHNOLOGIES AG

WAFER, ELECTRONIC COMPONENT AND METHOD USING LASER PENETRATION AFFECTING STRUCTURE

PARALLEL ELECTRIC PATHS WITH ELECTRONIC DEVICES AND CURRENT LIMITING CIRCUITS

RIVET FOR USE IN SEMICONDUCTOR MODULE ARRANGEMENT, METHOD FOR PRODUCING A RIVET, AND METHOD FOR CONNECTING RIVET TO A SUBSTRATE

DIFFUSION SOLDERING METHOD AND SOLDER MATERIAL

ELECTRONIC SYSTEM HAVING INTERMETALLIC CONNECTION STRUCTURE WITH CENTRAL INTERMETALLIC MESH STRUCTURE AND MESH-FREE EXTERIOR STRUCTURES

METHOD FOR MANUFACTURING A CHIP PACKAGE, CHIP PACKAGE, WAFER STRUCTURE, AND METHOD FOR PROCESSING A CHIP PACKAGE COMPONENT

SOLDERING METHOD

SEMICONDUCTOR PACKAGES INCLUDING A PACKAGE BODY WITH GROOVES FORMED THEREIN

SEMICONDUCTOR PACKAGE COMPRISING A FASTENING DEVICE FOR FAS-TENING THE SEMICONDUCTOR PACKAGE TO A HEAT SINK

METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE, DIE, AND DIE PACKAGE

RIVET FOR USE IN SEMICONDUCTOR MODULE ARRANGEMENT AND METHOD FOR PRODUCING THE SAME

SEMICONDUCTOR MODULE COMPRISING A HOUSING

ELECTRONIC COMPONENT SEPARATED FROM WAFER BY BACK SIDE GROOVE AND GROOVE EXTENSION

ELECTRONIC COMPONENT WITH STACKED BARRIER STRUCTURE, INTERMEDIATE STRUCTURE COMPRISING NICKEL, AND COPPER AND/OR ALUMINIUM STRUCTURE

SEMICONDUCTOR MODULE ARRANGEMENT, AND METHODS FOR PRODUCING SEMICONDUCTOR MODULE ARRANGEMENTS

WIRE BONDING TOOL

SEMICONDUCTOR MODULE AND A METHOD FOR FORMING THE SAME

PACKAGE WITH CARRIER HAVING COMPONENT ON PAD ON ONE SIDE AND OTHER PAD WITH TWO METALLIC AREAS ON OTHER SIDE

SEMICONDUCTOR DEVICES, LEADFRAMES, SYSTEMS AND ASSOCIATED MANUFACTURING METHODS

DIAGNOSIS OF ELECTRICAL FAILURES IN CAPACITIVE SENSORS

PACKAGE MANUFACTURABLE USING THERMOPLASTIC STRUCTURE COVERING A COMPONENT ASSEMBLY SECTION WITHOUT COVERING A LEAD SECTION

ENCAPSULATED PACKAGE HAVING TIE BAR EXPOSED AT STEPPED SIDEWALL WITH NOTCH

ENCAPSULATED PACKAGE WITH CARRIER HAVING TIE BAR VERTICALLY COVERED BY ENCAPSULANT

METHOD OF FORMING A DIE PACKAGE AND DIE PACKAGE ARRANGEMENT

SEMICONDUCTOR DEVICE INCLUDING A COINED DIEPAD

CHIP SEPARATION SUPPORTED BY BACK SIDE TRENCH AND ADHESIVE THEREIN

SEMICONDUCTOR PACKAGES AND ASSOCIATED MANUFACTURING METHODS

ENCAPSULATED PACKAGE WITH CARRIER HAVING RETRACTED LATERAL EXTENSION LATERALLY COVERED BY ENCAPSULANT

DIE ATTACH STRUCTURE, SEMICONDUCTOR PACKAGE, METHOD OF FORMING A DIE ATTACH STRUCTURE, METHOD OF FORMING A SEMICONDUCTOR PACKAGE, METAL LAYER STACK AND METHOD OF FORMING A METAL LAYER STACK

LEADFRAME PANEL, A SEMICONDUCTOR PACKAGE COMPRISING A LEADFRAME WITH A TWO-LEVEL DAMBAR DESIGN AND A METHOD FOR FABRICATING THE SAME

HOUSING, SEMICONDUCTOR MODULE COMPRISING A HOUSING, AND METHOD FOR ASSEMBLING A SEMICONDUCTOR MODULE

PACKAGE WITH CARRIER HAVING COMPONENT ACCOMMODATION VOLUME ON ONE SIDE AND REPELLING STRUCTURE ON OTHER SIDE

ENCAPSULANT WITH LOW CTE AND LOW YOUNG MODULUS FOR LOW-STRESS ELECTRONIC PACKAGE

TEST PIN WITH POGO PIN AND SURROUNDING COIL SPRING FOR TESTING DEVICES UNDER TEST

METAL COMPONENT INCLUDING AN INTERMETALLIC COMPOUND LAYER AND METHOD FOR MANUFACTURING THEREOF

HOUSING FOR A SEMICONDUCTOR MODULE, SEMICONDUCTOR MODULE COMPRISING A HOUSING, AND METHOD FOR ASSEMBLING A SEMICONDUCTOR MODULE COMPRISING A HOUSING

METHOD OF EMBEDDING AN EMBEDDABLE OBJECT INTO A STACKED SUBSTRATE AND STACKED SUBSTRATE ARRANGEMENT

PACKAGE WITH CARRIER HAVING PLATED BOTTOM SURFACE AND SIDEWALL

PACKAGE WITH COMPONENT-CARRYING INTERMEDIATE STRUCTURE AND ADDITIONAL CARRIER HAVING REFERENCE POTENTIAL STRUCTURE

SEMICONDUCTOR DEVICE COMPRISING A CARRIER, A SEMICONDUCTOR DIE AND A C-SHAPED CLIP CONNECTED BETWEEN THEM

POWER STAGE PACKAGE WITH HALF BRIDGE-CONNECTED TRANSISTOR CHIPS AND DRIVER CHIP HAVING THROUGH CONNECTION

ENCAPSULATED PACKAGE WITH CARRIER, LAMINATE BODY AND COMPONENT IN BETWEEN

ENCAPSULANT WITH ORGANIC CONSTITUENT AND INORGANIC CONSTITUENT HAVING ADJUSTED RELATIVE DIELECTRIC CONSTANT