San Jose, California
United States
26
2017-08-01
The entities that hold a legal rights for patent applications filed by inventor Schultz David P.:
David P. Schultz from San Jose, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Circuit arrangement for and a method of enabling a partial reconfiguration of a circuit implemented in an integrated circuit device
#2 | 2012-10-30Error checking parity and syndrome of a block of data with relocated parity bits
#3 | 2012-08-14Error checking parity and syndrome of a block of data with relocated parity bits
#4 | 2012-07-17Method and apparatus for implementing a cyclic redundancy check circuit
#5 | 2012-01-17Method of and circuit for generating a random number using a multiplier oscillation
#6 | 2011-12-08Input/output bank architecture for an integrated circuit
#7 | 2011-02-22Error checking parity and syndrome of a block of data with relocated parity bits
#8 | 2009-05-05Method of selectively programming integrated circuits to compensate for process variations and/or mask revisions
#9 | 2008-09-30Error correction for multiple word read
#10 | 2008-09-16Error checking parity and syndrome of a block of data with relocated parity bits
#11 | 2008-05-06Programmable integrated circuit with selective programming to compensate for process variations and/or mask revisions
#12 | 2008-01-01Method and system for configuring an integrated circuit
#13 | 2007-10-23Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testability
#14 | 2007-10-16Data monitoring for single event upset in a programmable logic device
#15 | 2007-03-27Method and apparatus for a multiplexed address line driver
#16 | 2006-11-28Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testability
#17 | 2006-09-19Data monitoring for single event upset in a programmable logic device
#18 | 2006-09-19Method and system for flexibly nesting JTAG TAP controllers for FPGA-based system-on-chip (SoC)
#19 | 2006-09-14Arithmetic logic unit circuit
#20 | 2006-08-24Digital signal processing element having an arithmetic logic unit
#21 | 2005-11-10Reconfiguration port for dynamic reconfiguration
#22 | 2005-11-03Reconfiguration port for dynamic reconfiguration-system monitor interface
#23 | 2005-11-03Boundary-scan circuit used for analog and digital testing of an integrated circuit
#24 | 2005-11-03Reconfiguration port for dynamic reconfiguration-controller
#25 | 2005-11-03Reconfiguration port for dynamic reconfiguration—sub-frame access for reconfiguration
#26 | 2005-02-24Programmable gate array and embedded circuitry initialization and processing
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