Gyeonggi-do
South Korea
18
2011-12-22
The entities that hold a legal rights for patent applications filed by inventor CHO Hye-Jin:
Hye-Jin CHO from Gyeonggi-do, KR has applied for patents for these inventions. The list has both pending applications and granted patents:
Nonvolatile memory device having stacked semiconductor layers and common source line adjacent to bit line plug
#2 | 2010-04-29Methods of fabricating vertical twin-channel transistors
#3 | 2009-12-24Nonvolatile memory device
#4 | 2009-10-08Methods of manufacturing non-volatile memory devices
#5 | 2009-06-11Semiconductor packages
#6 | 2008-04-03Methods of Manufacturing Non-Volatile Memory Devices
#7 | 2008-02-14Semiconductor devices having field effect transistors
#8 | 2008-02-07Vertical Twin-Channel Transistors and Methods of Fabricating the Same
#9 | 2008-01-03Metal oxide semiconductor (MOS) transistors having three dimensional channels
#10 | 2007-08-16Methods of Manufacturing Semiconductor devices Having Buried Bit Lines
#11 | 2006-12-28Metal oxide semiconductor (MOS) transistors having buffer regions below source and drain regions
#12 | 2006-10-17Methods of fabrication metal oxide semiconductor (MOS) transistors having buffer regions below source and drain regions
#13 | 2006-06-22Semiconductor devices having buried bit lines and methods of manufacturing semiconductor devices having buried bit lines
#14 | 2005-12-08Methods of fabricating fin field transistors
#15 | 2005-07-21Semiconductor devices having field effect transistors
#16 | 2005-04-14Methods of forming multi fin FETs using sacrificial fins and devices so formed
#17 | 2005-03-24Field effect transistors including vertically oriented gate electrodes extending inside vertically protruding portions of a substrate
#18 | 2005-02-10Methods of forming metal oxide semiconductor (MOS) transistors having three dimensional channels
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