Chung H. Lam

Integration of selector on confined phase change memory

Integration of selector on confined phase change memory

Neuron peripheral circuits for neuromorphic synaptic memory array based on neuron models

Writing multiple levels in a phase change memory

Writing multiple levels in a phase change memory

Writing multiple levels in a phase change memory

Writing multiple levels in a phase change memory

Crystallized silicon vertical diode on BEOL for access device for confined PCM arrays

Crystallized silicon vertical diode on BEOL for access device for confined PCM arrays

Writing multiple levels in a phase change memory

Writing multiple levels in a phase change memory

Crystallized silicon vertical diode on BEOL for access device for confined PCM arrays

Phase change memory array with integrated polycrystalline diodes

Phase change memory array with integrated polycrystalline diodes

Writing multiple levels in a phase change memory

Writing multiple levels in a phase change memory

Integration of confined phase change memory with threshold switching material

Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices

Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices

Writing multiple levels in a phase change memory

Neuromorphic memory circuit

System to duplicate neuromorphic core functionality

Asymmetric finFET memory access transistor

FinFET PCM access transistor having gate-wrapped source and drain regions

FinFET PCM access transistor having gate-wrapped source and drain regions

Asymmetric finFET memory access transistor

Phase change memory with an incrementally ramped write-reference voltage and an incrementally ramped read-reference voltage

Communicating postsynaptic neuron fires to neuromorphic cores

Neuron peripheral circuits for neuromorphic synaptic memory array based on neuron models

Neuron peripheral circuits for neuromorphic synaptic memory array based on neuron models

Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices

Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices

Neuromorphic memory circuit using a leaky integrate and fire (LIF) line to transmit axon LIF pulse and a conductive denrite LIF line

Neuromorphic memory circuit using a dendrite leaky integrate and fire (LIF) charge

PHASE CHANGE MEMORY WITH METASTABLE SET AND RESET STATES

PHASE CHANGE MEMORY WITH METASTABLE SET AND RESET STATES

Writing multiple levels in a phase change memory using a write/read reference voltage ramping up over a write/read period

Writing multiple levels in a phase change memory

Symmetrical bipolar junction transistor array

Memory with mixed cell array and system including the memory

Memory device with memory buffer for premature read protection

Writing multiple levels in a phase change memory using a write reference voltage that incrementally ramps over a write period

Phase change memory cell with heat shield

Drift mitigation for multi-bits phase change memory

Self-aligned patterning technique for semiconductor device features

Self-aligned patterning technique for semiconductor device features

Phase change memory cell with large electrode contact area

Resistive memory with a stabilizer

Resistive memory with a stabilizer

Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor

Adaptive reference tuning for endurance enhancement of non-volatile memories

Adaptive reference tuning for endurance enhancement of non-volatile memories

Structure and fabrication of memory array with epitaxially grown memory elements and line-space patterns

Memory array with self-aligned epitaxially grown memory elements and annular FET

SELF-ALIGNED APPROACH FOR DRAIN DIFFUSION IN FIELD EFFECT TRANSISTORS

Structure and fabrication of memory array with epitaxially grown memory elements and line-space patterns

Memory array with self-aligned epitaxially grown memory elements and annular FET

SELF-ALIGNED APPROACH FOR DRAIN DIFFUSION IN FIELD EFFECT TRANSISTORS

Electrical coupling of memory cell access devices to a word line

Memory state sensing based on cell capacitance

Memory state sensing based on cell capacitance

SINGLE-MASK SPACER TECHNIQUE FOR SEMICONDUCTOR DEVICE FEATURES

Electrical coupling of memory cell access devices to a word line

Phase change memory cell with heat shield

Vertical surround gate formation compatible with CMOS integration

Phase change memory cell with large electrode contact area

Phase change memory cell with large electrode contact area

Three-dimensional memory array and operation scheme

Three-dimensional memory array and operation scheme

Uniform critical dimension size pore for PCRAM application

Reliable physical unclonable function for device authentication

Reliable physical unclonable function for device authentication

Reactive material for integrated circuit tamper detection and response

Multi-bit resistance measurement

Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor

Method of reducing system power with mixed cell memory array

Memory controller for memory with mixed cell array and method of controlling the memory

Memory with mixed cell array and system including the memory

Memory controller for memory with mixed cell array and method of controlling the memory

Single-mask spacer technique for semiconductor device features

Writing scheme for phase change material-content addressable memory

Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor

Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming

Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming

Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor

Drift-insensitive or invariant material for phase change memory

Drift-insensitive or invariant material for phase change memory

Thermally insulated phase change material cells

METHOD TO TAILOR LOCATION OF PEAK ELECTRIC FIELD DIRECTLY UNDERNEATH AN EXTENSION SPACER FOR ENHANCED PROGRAMMABILITY OF A PROMPT-SHIFT DEVICE

Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor

Writing scheme for phase change material-content addressable memory

Decoding scheme for bipolar-based diode three-dimensional memory requiring bipolar programming

Sense scheme for phase change material content addressable memory

Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor

Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor

Parallel programming scheme in multi-bit phase change memory

Drift mitigation for multi-bits phase change memory

Energy-efficient row driver for programming phase change memory

Memory cell with post deposition method for regrowth of crystalline phase change material

HEAT SHIELD LINER IN A PHASE CHANGE MEMORY CELL