Chandler, Arizona
United States
38
2018-02-13
The entities that hold a legal rights for patent applications filed by inventor Miner David E.:
David E. Miner from Chandler, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Method and apparatus for use of a preload instruction to improve efficiency of cache
#2 | 2015-07-21Method and apparatus for associating requests and responses with identification information
#3 | 2015-03-24Cache memory bank selection
#4 | 2014-07-01Programmable cache access protocol to optimize power consumption and performance
#5 | 2014-04-01Method and apparatus for associating requests and responses with identification information
#6 | 2013-09-10Implementing direct access caches in coherent multiprocessors
#7 | 2013-06-04Programmable cache access protocol to optimize power consumption and performance
#8 | 2012-10-23Method and apparatus for data-less bus query
#9 | 2012-03-13Method and apparatus for hardware-configurable multi-policy coherence protocol
#10 | 2011-06-21Power optimized replay of blocked operations in a pipilined architecture
#11 | 2010-07-27Apparatus and method for arbitrating heterogeneous agents in on-chip busses
#12 | 2010-07-13Method and apparatus for optimizing line writes in cache coherent systems
#13 | 2010-02-25Test access port
#14 | 2008-12-09Method and apparatus for supporting opportunistic sharing in coherent multiprocessors
#15 | 2008-11-13System and apparatus for early fixed latency subtractive decoding
#16 | 2008-10-09Method and apparatus for implementing heterogeneous interconnects
#17 | 2007-10-30Cache memory to support a processor's power mode of operation
#18 | 2007-08-09System and apparatus for early fixed latency subtractive decoding
#19 | 2007-07-12Systems and methods for early fixed latency subtractive decoding including speculative acknowledging
#20 | 2007-06-19Power/performance optimized cache using memory write prevention through write snarfing
#21 | 2007-05-15System and apparatus for early fixed latency subtractive decoding
#22 | 2006-11-30Apparatus and method for arbitrating heterogeneous agents in on-chip busses
#23 | 2006-11-21Test access port
#24 | 2006-11-02Test access port
#25 | 2006-08-29Methods and apparatus for cache intervention
#26 | 2006-06-29Method and apparatus for implementing heterogeneous interconnects
#27 | 2006-05-25Techniques for pushing data to a processor cache
#28 | 2006-01-05Direct processor cache access within a system having a coherent multi-processor protocol
#29 | 2006-01-05Direct processor cache access within a system having a coherent multi-processor protocol
#30 | 2006-01-03Methods and apparatus for cache intervention
#31 | 2005-12-29Pushing of clean data to one or more processors in a system having a coherency protocol
#32 | 2005-09-29Apparatus and method for granting concurrent ownership to support heterogeneous agents in on-chip busses having different grant-to-valid latencies
#33 | 2005-09-15Cache memory to support a processor's power mode of operation
#34 | 2005-09-15Cache memory to support a processor's power mode of operation
#35 | 2005-09-01Cache memory to support a processor's power mode of operation
#36 | 2005-07-28Methods and apparatus for cache intervention
#37 | 2005-06-09Methods and apparatus to dispatch interrupts in multi-processor systems
#38 | 2005-03-31Apparatus and method for power optimized replay via selective recirculation of instructions
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