William E. Burky

Processor and method for partially flushing a dispatched instruction group including a mispredicted branch

Selective Execution Dependency Matrix

Dependency Matrix with Improved Performance

Tracking deallocated load instructions using a dependence matrix

Information handling system with real and virtual load/store instruction issue queue

Configuring plural cores to perform an instruction having a multi-core characteristic

Issuing load-dependent instructions in an issue queue in a processing unit of a data processing system

Structure for implementing speculative clock gating of digital logic circuits

Apparatus and method for implementing speculative clock gating of digital logic circuits

System and Method for Issuing Load-Dependent Instructions from an Issue Queue in a Processing Unit

Method and system for tracking instruction dependency in an out-of-order processor

Method And Apparatus For Register Renaming Using Multiple Physical Register Files And Avoiding Associative Search

Dynamically shared group completion table between multiple threads

Method for resource balancing using dispatch flush in a simultaneous multithread processor

Using a Register File as Either a Rename Buffer or an Architected Register File

Method and system for dependency tracking and flush recovery for an out-of-order microprocessor

METHOD AND SYSTEM FOR ON-DEMAND SCRATCH REGISTER RENAMING

Method For Changing A Thread Priority In A Simultaneous Multithread Processor

Method for changing a thread priority in a simultaneous multithread processor

Method and apparatus for register renaming using multiple physical register files and avoiding associative search

Method and system for on-demand scratch register renaming

Method using a dispatch flush in a simultaneous multithread processor to resolve exception conditions

SMT flush arbitration