Christopher Michael Abernathy

Instruction tracking system for processors

Selecting fixed-point instructions to issue on load-store unit

Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines

Dynamic power management in an execution unit using pipeline wave flow control

Time-of-life counter for handling instruction flushes from a queue

Method and apparatus for register renaming

Dynamic power management in a processor design

Queue design system supporting dependency checking and issue for SIMD instructions within a general purpose processor

Method and apparatus for correcting data errors

Generating a flush vector from a first execution unit directly to every other execution unit of a plurality of execution units in order to block all register updates

Method and apparatus for issuing instructions from an issue queue including a main issue queue array and an auxiliary issue queue array in an information handling system

System and method for dynamically selecting storage instruction performance scheme

Time-of-life counter design for handling instruction flushes from a queue

Queue design supporting dependency checking and issue for SIMD instructions within a general purpose processor

Dynamic power management in a processor design

Method and apparatus for issuing instructions from an issue queue in an information handling system

Method and apparatus for dynamic power management in an execution unit using pipeline wave flow control

Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines

Fine grained multi-thread dispatch block mechanism

Method and apparatus for dynamic power management in an execution unit using pipeline wave flow control

Method and system for performing shift operations