Newburgh, New York
United States
42
2015-07-30
The entities that hold a legal rights for patent applications filed by inventor Yan Jiang:
Jiang Yan from Newburgh, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Method for making HKMG dummy gate structure with amorphous/ONO masking structure and procedure
#2 | 2015-02-05Method for manufacturing dummy gate in gate-last process and dummy gate in gate-last process
#3 | 2015-01-01Silicided semiconductor structure and method of forming the same
#4 | 2014-11-13Method for manufacturing dummy gate in gate-last process and dummy gate in gate-last process
#5 | 2014-09-18Method for manufacturing dummy gate in gate-last process and dummy gate in gate-last process
#6 | 2014-01-16Method for Forming Gate Structure, Method for Forming Semiconductor Device, and Semiconductor Device
#7 | 2013-12-05Mixed orientation semiconductor device and method
#8 | 2013-04-04Silicon-on-insulator chip having multiple crystal orientations
#9 | 2013-03-07Method of manufacturing dummy gates in gate last process
#10 | 2013-03-07METHOD FOR MANUFACTURING ELECTRODES AND WIRES IN GATE LAST PROCESS
#11 | 2013-01-24Semiconductor device, formation method thereof, and package structure
#12 | 2013-01-17Transistor, Semiconductor Device, and Method for Manufacturing the Same
#13 | 2012-12-20Method for monitoring the removal of polysilicon pseudo gates
#14 | 2012-08-02Method for manufacturing contact holes in CMOS device using gate-last process
#15 | 2012-05-24Strained semiconductor device and method of making same
#16 | 2011-07-21Methods of Forming Conductive Features and Structures Thereof
#17 | 2011-01-13Transistor Structure
#18 | 2010-11-25Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same
#19 | 2010-08-05Silicided semiconductor structure and method of forming the same
#20 | 2010-06-17Methods of operating embedded flash memory devices
#21 | 2010-04-22Strained semiconductor device and method of making same
#22 | 2010-02-04Methods of Forming Electrical Interconnects Using Thin Electrically Insulating Liners in Contact Holes
#23 | 2009-12-03Methods of forming conductive features and structures thereof
#24 | 2009-12-03Transistor fabrication methods and structures thereof
#25 | 2009-12-03Methods of Fabricating Transistors and Structures Thereof
#26 | 2009-05-28Embedded flash memory devices on SOI substrates and methods of manufacture thereof
#27 | 2008-12-11Semiconductor devices and methods of manufacturing thereof
#28 | 2008-10-09SILICIDE FORMATION FOR eSiGe USING SPACER OVERLAPPING eSiGe AND SILICON CHANNEL INTERFACE AND RELATED PFET
#29 | 2008-05-22Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same
#30 | 2008-05-15Forming conductive stud for semiconductive devices
#31 | 2008-05-15Forming conductive stud for semiconductive devices
#32 | 2008-04-17Pre-silicide spacer removal
#33 | 2008-04-17Post-silicide spacer removal
#34 | 2008-04-17Strained semiconductor device and method of making same
#35 | 2008-03-27Semiconductor device and method of making same
#36 | 2008-03-06Self-aligned dual segment liner and method of manufacturing the same
#37 | 2008-01-31Semiconductor method and device with mixed orientation substrate
#38 | 2007-08-16Method for fabricating a semiconductor device with a high-K dielectric
#39 | 2007-06-28Mixed orientation semiconductor device and method
#40 | 2007-06-28Silicon-on-insulator chip having multiple crystal orientations
#41 | 2007-03-15Embedded flash memory devices on SOI substrates and methods of manufacture thereof
#42 | 2006-08-03Semiconductor method and device with mixed orientation substrate
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