Austin, Texas
United States
29
2023-03-09
The entities that hold a legal rights for patent applications filed by inventor Cargnoni Robert Alan:
Robert Alan Cargnoni from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Logical clock connection in an integrated circuit design
#2 | 2010-10-21Load request scheduling in a cache hierarchy
#3 | 2010-08-24Cache coherent I/O communication
#4 | 2009-12-31Information handling system including a multiple compute element processor with distributed data on-ramp data-off ramp topology
#5 | 2009-06-18Enhanced processor virtualization mechanism via saving and restoring soft processor/system states
#6 | 2009-02-17Method and data processing system for microprocessor communication using a processor interconnect in a multi-processor system
#7 | 2009-02-17Enhanced processor virtualization mechanism via saving and restoring soft processor/system states
#8 | 2008-06-26Method and data processing system for processor-to-processor communication in a clustered multi-processor system
#9 | 2008-05-08Method, processing unit and data processing system for microprocessor communication in a multi-processor system
#10 | 2008-04-17Method and data processing system for microprocessor communication in a cluster-based multi-processor system
#11 | 2008-04-15Method and data processing system for microprocessor communication in a cluster-based multi-processor system
#12 | 2008-04-15Method and data processing system for microprocessor communication in a cluster-based multi-processor wireless network
#13 | 2008-04-08Method, processing unit and data processing system for microprocessor communication in a multi-processor system
#14 | 2007-09-18Cache directory array recovery mechanism to support special ECC stuck bit matrix
#15 | 2007-09-18Cross partition sharing of state information
#16 | 2006-10-03Managing processor architected state upon an interrupt
#17 | 2006-09-05Cache allocation mechanism for biasing subsequent allocations based upon cache directory state
#18 | 2006-06-27Application of special ECC matrix for solving stuck bit faults in an ECC protected mechanism
#19 | 2006-05-30Data cache scrub mechanism for large L2/L3 data cache structures
#20 | 2006-05-30Integrated purge store mechanism to flush L2/L3 cache structure for improved reliabity and serviceability
#21 | 2006-05-16Data processing system providing hardware acceleration of input/output (I/O) communication
#22 | 2006-05-11Method, system, and program for transferring data directed to virtual memory addresses to a device memory
#23 | 2006-05-02Robust system reliability via systolic manufacturing level chip test operating real time on microprocessors/systems
#24 | 2006-02-07Cache allocation mechanism for saving multiple elected unworthy members via substitute victimization and imputed worthiness of multiple substitute victim members
#25 | 2006-01-03Dynamically managing saved processor soft states
#26 | 2005-12-27Processor virtualization mechanism via an enhanced restoration of hard architected states
#27 | 2005-12-13Acceleration of input/output (I/O) communication through improved address translation
#28 | 2005-11-10System and method to stall dispatch of gathered store operations in a store queue using a timer
#29 | 2005-09-27Method and system for managing distributed arbitration for multicycle data transfer requests
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