Austin, Texas
United States
27
2009-03-19
The entities that hold a legal rights for patent applications filed by inventor DeMent Jonathan James:
Jonathan James DeMent from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines
#2 | 2009-03-19Bus controller initiated write-through mechanism with hardware automatically generated clean command
#3 | 2009-02-12Time-of-life counter for handling instruction flushes from a queue
#4 | 2009-01-15System and method for cache-locking mechanism using segment table attributes for replacement class ID determination
#5 | 2009-01-15System and method for cache-locking mechanism using translation table attributes for replacement class ID determination
#6 | 2008-09-18Dynamic power management in a processor design
#7 | 2008-07-10Queue design system supporting dependency checking and issue for SIMD instructions within a general purpose processor
#8 | 2008-06-19High Frequency Stall Design
#9 | 2007-12-13METHOD AND APPARATUS FOR POWER MANAGEMENT IN A DATA PROCESSING SYSTEM
#10 | 2007-10-25Pseudo-LRU virtual counter for a locking cache
#11 | 2007-08-23Method and apparatus for issuing instructions from an issue queue including a main issue queue array and an auxiliary issue queue array in an information handling system
#12 | 2007-05-24System and method for dynamically selecting storage instruction performance scheme
#13 | 2007-04-12Time-of-life counter design for handling instruction flushes from a queue
#14 | 2007-04-12Queue design supporting dependency checking and issue for SIMD instructions within a general purpose processor
#15 | 2007-03-29Dynamic power management in a processor design
#16 | 2007-03-29Method and apparatus for issuing instructions from an issue queue in an information handling system
#17 | 2007-02-22System and method for high frequency stall design
#18 | 2007-01-25Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines
#19 | 2006-12-21Fine grained multi-thread dispatch block mechanism
#20 | 2006-10-05System and method for handling multi-cycle non-pipelined instruction sequencing
#21 | 2006-02-16Bus controller initiated write-through mechanism
#22 | 2005-08-18Method of effective to real address translation for a multi-threaded microprocessor
#23 | 2005-07-21Method and apparatus for preloading translation buffers
#24 | 2005-06-09Method of efficiently handling multiple page sizes in an effective to real address translation (ERAT) table
#25 | 2005-04-21Time-base implementation for correcting accumulative error with chip frequency scaling
#26 | 2005-03-10Pseudo-LRU for a locking cache
#27 | 2005-02-03Translation look-aside buffer sharing among logical partitions
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