Navneet Dour

City:

Folsom, California

Country:

United States

Published Applications:

Last publication date:

2009-04-02

Top Assignees for applications by Navneet Dour

The entities that hold a legal rights for patent applications filed by inventor Dour Navneet:

INTEL CORPORATION 8 Santa Clara, CA United States

Recent patent applications by Dour Navneet

Navneet Dour from Folsom, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2009-04-02

US20090085618A1

Electricity

Wake-up circuit

#2 | 2008-03-13

US20080065922A1

Physics

Extended synchronized clock

#3 | 2007-01-11

US20070007992A1

Physics

Method and apparatus to calibrate DRAM on resistance (Ron) and on-die termination (ODT) values over process, voltage and temperature (PVT) variations

#4 | 2006-11-02

US20060245519A1

Electricity

Calibrating integrating receivers for source synchronous protocol

#5 | 2006-11-02

US20060245473A1

Physics

Integrating receivers for source synchronous protocol

#6 | 2006-06-08

US20060119381A1

Electricity

PVT controller for programmable on die termination

#7 | 2006-06-01

US20060114742A1

Physics

Method and apparatus for optimizing strobe to clock relationship

#8 | 2006-01-05

US20060002482A1

Physics

Signal drive de-emphasis for memory bus

#9 | 2005-09-08

US20050194991A1

Electricity

Method and apparatus for PVT controller for programmable on die termination

#10 | 2005-08-25

US20050185480A1

Physics

Dynamically activated memory controller data termination

InventorID:

3914991 ⎘