Gyeonggi-do
South Korea
12
2009-08-06
The entities that hold a legal rights for patent applications filed by inventor Ku Ja-hum:
Ja-hum Ku from Gyeonggi-do, KR has applied for patents for these inventions. The list has both pending applications and granted patents:
CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein
#2 | 2009-05-14Methods of forming CMOS integrated circuits that utilize insulating layers with high stress characteristics to improve NMOS and PMOS transistor carrier mobilities
#3 | 2009-01-15Methods for removing gate sidewall spacers in CMOS semiconductor fabrication processes
#4 | 2008-10-02Methods of forming CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein and circuits formed thereby
#5 | 2008-05-29Methods of Forming CMOS Integrated Circuits Using Gate Sidewall Spacer Reduction Techniques
#6 | 2008-05-22CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities and Methods of Forming Same
#7 | 2008-02-07Semiconductor Device Having a Dual Stress Liner and Light Exposure Apparatus for Forming the Dual Stress Liner
#8 | 2007-08-09Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics
#9 | 2007-04-12Methods of fabricating semiconductor devices having a dual stress liner
#10 | 2006-07-27Methods of forming a semiconductor device having a metal gate electrode and associated devices
#11 | 2005-03-08Methods of fabricating integrated circuit gates by pretreating prior to oxidizing
#12 | 2005-01-27Methods of forming a semiconductor device having a metal gate electrode and associated devices
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